Q2: Design a FSM that in its output is showing the output of a 2x4 decoder in sequence if input is 1 and remain on the same state and output if the input is 0: A- Draw the state diagram? B- How many bits you need for the state code? C- Is it Mealy or Moor model and why? D- Design the logic circuit of this FSM using JK flip flop?

The truth table for a Boolean expression is shown on figure1.  A, B, C, D are inputs and Y is the output Write the Boolean expression on SOP form Y = f (A, B, C, D) Minimize the function using Karnaugh Map (K Map) Draw the minimized function using logic gates