B- A- B-[ A B -Y -Y AHC AH A B- B (a) 1. Write a truth table for the function performed by the gate in figures above. (b) 2. Sketch a transistor-level circuit for the following CMOS gates. (a) Two input OR gate (b) Three-input AND gate
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- using only nand gates and inverters and alternate symbols where appropriate, draw the logic for the equation: F(A,B,C) = Em(3,4,5,6,7) + Ed(0)Assume Vth = 1V and k = 50mA/V2. Given the schematic below, do the following: 1) Indicate and verify the state of each MOSFET and ?0 for the following input combinations. Fill-out the table below for each assumed state of the MOSFET for every input combination. Use ?ds,on approximation for linear operation. 2) Determine what kind of logic circuit is implemented in the circuit.Digital Logic Design [1] Simplify the following functions, and implement them with two-level NOR gate circuits:(a) ? = ??' + ?' ?' + ?'??'(b) ? ?, ?, ?, ? = 1, 2, 13, 14[2] (a) Implement the following function using NAND gates with a fan in of 2. F = (ab + d')(ac + b) + (ac +b)d (b) Simplify the above function and implement using NAND gates with a fan in of 2.
- What are the delay and power-delay product for the ECL gate as shown if IEE is changed to 0.5 mA, but the logic swing is maintained the same?Q1: Can the function Z be designed using single gate ? In any case design a circuit that implements the function Z with minimum CMOS gates.1-Consider a 4-input NOR gate that consists of 2, 2-input NOR gates whose outputs are combined by a 2-input NAND gate, followed by an inverter. What is the minimum possible delay for a 50C load and a standard size NOR gates (X1)? 2- What are the sizes of all the transistors for problem 1?
- 1) Draw how an ASIC, SOC, MCU, MPU, DSP any TTL gates of the TTL circuits you have constructed or designed to use a transistor (BJT/MOS) to drive the current specification of a LOAD (ie RELAY, Motor, Light array of High powered LEDs)Draw the schematic for a four-input NOR gate witha saturated load device. What are the W/L ratios ofall the transistors, based on the reference inverter ? (b) What is VL if all the logic inputs are equal to 1?How would you manipulate this equation to get it into a format where you can draw it as a NAND and inverter gates logic diagram and a NOR and inverter gates logic diagram?
- 4. What will be the minimum number of 2-input NAND gates required implement the following expression? (EXPRESSION IN PICTURE ATTACHED)Question (1): In following circuit employing pass transistor logic ,all NMOS transistor are identical with theresold voltage of? V, Ignoring the vody effect, the output out-put voltage at p, q, r are hinds? V=1v Question (2): Evaluate the mode of operation and drain current of an Enhancement type n-MOS for following parameters?Vt=1v , β/kn =0.5 ma/v2 and λ =0.02v-1 ,Vgs=2v , Vds=2vF A,B,C,D) = ∑ (1, 2, 3, 8, 9, 10, 11,14)× d (7, 15) Use Karnaugh map and Quinn McKlausky Method. Draw the logic circuit for the simplified function using NOR gates for both methods. Compare Both methods in terms of cost assuming a Nor gate costs 10 cents.