COMPUTER ARCHITECTURESuppose there are 10 processors on a bus that each try to lock avariable simultaneously. Assume that each bus transaction [readmiss or write miss] is 100 clock cycles long. You can ignore thetime of the actual read or write of a clock held in the cache, aswell as the time the lock is held. Determine that number of bustransactions required for all 10 processors to acquire the lock,assuming they are all spinning when the lock is released at time is0, about how long will it take to process the 10 re quests?Assume that the bus is totally fair so that every pending request isserviced before a'new request and that the processors areequally fast

Answered: COMPUTER ARCHITECTURE Suppose there are…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Take into account the following scenario: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Since there are 8 bytes in a block, you can use that information to calculate how big the offset field has to be.
Suppose we have a system with 8-byte words and a cache with 32-byte blocks connected directly to memory. The cache has a hit time of 10 ns. The bus to memory is 8 bytes wide, requesting a word from memory takes 100 ns (total, aka round trip time), and memory bus transactions are serialized (not pipelined). The baseline cache requests each word from memory sequentially on a miss, and waits to respond to the CPU until miss repair is fully complete. Consider a workload with poor locality, with a cache hit rate of only 20%. Show your work. (a) What is the AAT speedup of early restart over baseline? Assume a uniform distribution of accesses to each word in a block (25% chance of each). This means that 25% of misses are for word 1 in a block, 25% for word 2, 25% for word 3, and 25% for word 4. (b) What is the AAT speedup over baseline of early restart if the distribution of accesses to each word in a block is 5%, 15%, 30%, and 50%, respectively? (c) What is the AAT speedup over baseline with…
Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache
For a processor with a 32-bit address bus and a 64-bit data bus, 32 bytes of "line size" and a total capacity of 2MByte "cache" memory are used. For each of the "cache map" techniques given below, find how the physical address will be partitioned and how many bits will be used for each partition. a) 2-way set associative b) 4-way set associative
Suppose that a computer has a processor with two L1 caches, one for instructions and one for data, and an L2 cache. Let τ be the access time for the two L1 caches. Themiss penalties are approximately 15τ for transferring a block from L2 to L1, and 100τ fortransferring a block from the main memory to L2. For the purpose of this problem, assumethat the hit rates are the same for instructions and data and that the hit rates in the L1 andL2 caches are 0.96 and 0.80, respectively.(a) What fraction of accesses miss in both the L1 and L2 caches, thus requiring accessto the main memory?(b) What is the average access time as seen by the processor?(c) Consider the following change to the memory hierarchy. The L2 cache is removedand the size of the L1 caches is increased so that their miss rate is cut in half. Whatis the average memory access time as seen by the processor in this case
Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses.3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.
Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253 3.1 – For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty 3.2 – For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty
Computer Science Using snoopy MSI cache coherence protocol and given a table of three processes with time, how can I display each cache line and figure out what state it is in on every cycle if three professor are executing code that is interleaved? In the table there are just processes with LW and SW. Example: LW R8, 3(R1) Given: 128kbytes cache line block size. 8KB Direct mapped Cache
Suppose a byte-addressable computer using set associative cache has 4Mbyes of main memory and a cache of 64 blocks, where each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache? Show all work and explain how you got the answers please. Thanks
Caches are important to providing a high-performance memory hierarchy to processors.Below is a sequence of ten memory references in binary to an empty eight- one word blockcache. 10110,11010,10110,11010, 10000, 00011, 10000, 10010, 10000, 10111For each of these references tabulate the tag, valid bit status, the index, and the data givena direct-mapped cache. Also list if each reference is a hit or a miss, assuming the cache isinitially empty.
For a processor with a 32-bit address bus and a 64-bit data bus, 32 bytes of "line size" and a total capacity of 2MByte "cache" memory are used. For each of the "cache map" techniques given below, find how the physical address will be partitioned and how many bits will be used for each partition. a) fully associative b) direct mapped
Consider a computer with a single off-chip cache with a 10 ns hit time and a 95% hit rate. Mainmemory has an access time of 80 ns.I. What is the computer’s effective memory access time?II. Now, suppose, If we add a small on-chip direct mapped cache with a 1.4 ns hit time with60% hit rate, what is the computer’s effective memory access time?III. An alternative is to add a slightly larger 2-way associative on-chip cache with 2.1 ns hittime with 90% hit rate, what is the computer’s effective memory access time? IV. Which of the two alternatives is better? Determine the speedup achieved by the twoon-chip cache configurations (w.r.t. the baseline off-chip only cache)?

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