Consider a cache memory with blocks of 23 words (1 word = 4 bytes) , with a bus Main Memory - Cache of (23x 32) bits , and with 1 clock cycle to send the address, a row cycle time (DRAM) of 13 cycles (one column only) and 1 clock cycle to return a word. Calculate the bandwidth of the system in byte per clock cycles (bandwidth = number of bytes per clock cycles) for the transfer of one block from Main Memory to Cache Memory for an interleaved main memory system with 23 banks (width of any bank: one word). Provide the solution with at least 2 decimals

Consider a cache memory with blocks of 23 words (1 word = 4 bytes) , with a bus Main Memory - Cache of (23x 32) bits , and with 1 clock cycle to send the address, a row cycle time (DRAM) of 13 cycles (one column only) and 1 clock cycle to return a word. Calculate the bandwidth of the system in byte per clock cycles (bandwidth = number of bytes per clock cycles) for the transfer of one block from Main Memory to Cache Memory for an interleaved main memory system with 23 banks (width of any bank: one word). Provide the solution with at least 2 decimals

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 12RQ

See similar textbooks

Similar questions

Consider a cache memory with blocks of 23 = words (1 word = 4 bytes) , with a bus Main Memory - Cache of 32 bits, and with 1 clock cycle to send the address, a row cycle time (DRAM) of 17 cycles (5 less clock cycles for the column access time) and 1 clock cycle to return a word. Assuming that each word is in a different DRAM row, calculate the bandwidth of the system in byte per clock cycles (bandwidth = number of bytes per clock cycles) for the transfer of one block from Main Memory to Cache Memory (not interleaved memory system). Provide the solution with at least 2 decimals
Consider a memory system with a cache access time of 100ns and a memory access timeof 1200ns. If the effective access time is 10% greater than the cache access time, what is thehit ratio H?
Consider the following situation: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Based on the fact that each block has 8 bytes, figure out how big the offset field should be, and then show your work.
Consider a memory-management system based on paging. The total size of the physical address space 64 MB, Pages of size 4 KB, the Logical address space of 4GB. total number of pages are 16384, total number of frames are 16384 and the number of entries in a page table are 1048576.Now Calculate: a)Size of Page Table b) No of bits in Physical Address c) No of Bits in Logical Address
Suppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Suppose we have a system with 8-byte words and a cache with 32-byte blocks connected directly to memory. The cache has a hit time of 10 ns. The bus to memory is 8 bytes wide, requesting a word from memory takes 100 ns (total, aka round trip time), and memory bus transactions are serialized (not pipelined). The baseline cache requests each word from memory sequentially on a miss, and waits to respond to the CPU until miss repair is fully complete. Consider a workload with poor locality, with a cache hit rate of only 20%. Show your work. (a) What is the AAT speedup of early restart over baseline? Assume a uniform distribution of accesses to each word in a block (25% chance of each). This means that 25% of misses are for word 1 in a block, 25% for word 2, 25% for word 3, and 25% for word 4. (b) What is the AAT speedup over baseline of early restart if the distribution of accesses to each word in a block is 5%, 15%, 30%, and 50%, respectively? (c) What is the AAT speedup over baseline with…
Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache
Consider a process with 4GB logical memory, 4KB page size, and a page table whose entry is 4B each. The page table of this process will be placed in one of the cache memories to increase performance. The size of L1, L2, and L3 caches are 64KB, 256KB, and 8MB, respectively. Investigate which cache memory can we use to fully place the page table.
Consider a system with 2 level cache. Access times of Level 1 cache, Level 2 cache and main memory are 1 ns, 10 ns, and 500 ns, respectively. The hit rates of Level 1 and Level 2 caches are 0.8 and 0.9, respectively. What is the average access time of the system ignoring the search time within the cache?
Suppose a byte-addressable computer using set associative cache has 4Mbyes of main memory and a cache of 64 blocks, where each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache? Show all work and explain how you got the answers please. Thanks
Suppose a computer using set associative cache has 221 words of main memory and a cache of 64 blocks, where each cache block contains 4 words. a)If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and word fields? b)If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Suppose a two layer memory hierarchy has a 4 clock pulse hit time, a 35 clock pulse miss penalty, and the miss ratio is 20%. What is the AMAT (in number of clock pulses)?