Consider a machine which is byte addressable and has the segmented paging architecture for virtual memory. Virtual address space (VAS) is 4 GB and physical address space (PAS) is 4 GB. The VAS is divided into 128 non-overlapping equal size segments. The memory management unit (MMU) has a hardware segment table, each entry of which contains the physical address of the page table for the segment. Page tables are stored in the main memory and consists of 2- byte page table entries. The minimum page size in bytes so that the page table for a segment requires at most one page to store it КВ.

Consider a machine which is byte addressable and has the segmented paging architecture for virtual memory. Virtual address space (VAS) is 4 GB and physical address space (PAS) is 4 GB. The VAS is divided into 128 non-overlapping equal size segments. The memory management unit (MMU) has a hardware segment table, each entry of which contains the physical address of the page table for the segment. Page tables are stored in the main memory and consists of 2- byte page table entries. The minimum page size in bytes so that the page table for a segment requires at most one page to store it КВ.

Name: 3 Consider a machine which is byte addressableand has the segmented pa
Uploaded: 2024-03-20T06:51:23.000Z
Channel: Bartleby
Description: 3 Consider a machine which is byte addressableand has the segmented paging architecture forvirtual memory. Virtual address space (VAS) is 4GB and physical address space (PAS) is 4 GB.The VAS is divided into 128 non-overlappingequal size segments. The

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

Consider a processor that uses a 48-bit virtual memory address. The main memory installed onthe system is 4GB. Page size is set to be 32KB. Determine the following:I. Address space of virtual memory and physical memory. II. Total Number of virtual pages and the total physical pagesIII. How many bits are necessary to store (i) Page Table entry and (ii) TLB entry, consideringthe TLB entry stores valid, reference and dirty bits.IV. What is the size of the page table? And how many pages of memory is needed to storethe entire Page table? What fraction of physical memory is needed to store the entirepage table?
For an old computing system with 2K bytes physical memory, and the virtual address has 13bits. Suppose that the size of page/frame is 256 bytes. For a process A, it has its codes and data inpage 0, 1, 2, 10, 11, 28, 29, where pages 0, 1, 10, 29 are in frame 1, 3, 4 and 6, respectively.Moreover, frame 0 contains kernel OS code/data and all other frames are free.a. Show the page table and the content of each PTE for process A;b. Use a figure to illustrate the address translation for virtual address 1110000100000 and explainwhat happens during the translation (interaction among page table, physical memory, disk, andoperating system);c. Suppose that there is a TLB with 4 entries and the current content has the mapping informationfor pages 0, 1. Draw a new figure to illustrate the translation of address 101000011000 andexplain what happens during the translation process.
Suppose that a machine has 42-bit virtual addresses and 32-bit physical addresses.{a} How much RAM can the machine support (each byte of RAM must be addressable)?{b} What is the largest virtual address space that can be supported for a process?{c} If pages are 2 KB, how many entries must be in a single-level page table?{d} If pages are 2 KB and we have a two-level page table where the first level is indexed by 15-bits, then how many entries does the first-level page table have?{e} With the same setup as part {d}, how many entries are in each second-level page table?{f} What is the advantage of using a two-level page table over single-level page table?
Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?
Consider a computer system with a 64-bit logical address and 32-KB page size. Thesystem supports up to 4096 MB of physical memory. How many entries are there ineach of the following?a. A conventional single-level page table?b. An inverted page table?
In this exercise, we will examine space/time optimizations for page tables. The following list provides parameters of a virtual memory system. Virtual Address (bits) Physical DRAMInstalled Page Size PTE Size (byte) 43 16 GiB 4 KiB 4 For a single-level page table, how many page table entries (PTEs) are needed? How much physical memory is needed for storing the page table? Using a multilevel page table can reduce the physical memory consumption of page tables, by only keeping active PTEs in physical memory. How many levels of page tables will be needed in this case? And how many memory references are needed for address translation if missing in TLB? An inverted page table can be used to further optimize space and time. How many PTEs are needed to store the page table? Assuming a hash table implementation, what are the common case and worst case numbers of memory references needed for servicing a TLB miss?
Suppose a byte-addressable computer using set associative cache has 4Mbyes of main memory and a cache of 64 blocks, where each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache? Show all work and explain how you got the answers please. Thanks
Suppose a byte-addressable computer using set associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Consider a computer with 128 MB of main memory, 64 KB of cache, and 4 bytes per memory block. Find out how to split the address (s-r, r, w) so that it can be used for direct mapping.Find out how to split the address into two parts (s and w) for associative mapping.Find out how to split the address into three parts (s-d, d, and w) for set associative mapping. Assume that each cache set has two lines.
Suppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Suppose the page table for the process currently executing on the processor looks like the following. All numbers are decimal, everything is numbered starting from zero, and all addresses are memory byte addresses. The page size is 1,024 bytes. Virtual page number 0 Valid bit Reference bit Modify bit Page frame number 1 1 0 1 1 7 2 0 0 0 3 1 0 0 2 4 0 0 0 5 1 0 1 0 What physical address, if any, would each of the following virtual addresses correspond to? (Do not try to handle any page faults, if any.) 1,052 2,221 5,499 Edit View Insert 12pt Paragraph Format Tools Table BIU Av
Suppose we have a virtual address of 26 bits in a byte addressable machine. Page size is 8K bytes. Assume each page table entry is 4 bytes in this case. a. Design a two-level page table (Suppose we need to fit each page table into a physical frame). b. How many physical memory frames are needed to maintain the page tables for a process of 512KB?