Consdier a main memory with 32-bit addresses, access time of 100 clock cycles, and a cache in the memory hierarchy as described in the table below. a) How many bits in the 32-bit memory address are assigned for Tag, Index, and Offset? Please discuss and justify your answer. b)If we design this cache as a 4-way set associative cache, where we assume that the index field in the memory address becomes the set index, how would this change the number of bits for Tag, Index, and Offset in Question (a)? Please discuss and justify your answer.

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 Consdier a main memory with 32-bit addresses, access time of 100 clock cycles, and a cache in the memory hierarchy as described in the table below.

a) How many bits in the 32-bit memory address are assigned for Tag, Index, and Offset? Please discuss and justify your answer.

b)If we design this cache as a 4-way set associative cache, where we assume that the index field in the memory address becomes the set index, how would this change the number of bits for Tag, Index, and Offset in Question (a)? Please discuss and justify your answer.

Cache Size
32K Bytes
4 Bytes (1 word)
Direct-Mapped
Block Size
Cache Type
Hit Time
1 cycle
Miss Rate
5%
Number of bits in Tag
?
Number of bits in Index
?
Number of bits in Offset
Transcribed Image Text:Cache Size 32K Bytes 4 Bytes (1 word) Direct-Mapped Block Size Cache Type Hit Time 1 cycle Miss Rate 5% Number of bits in Tag ? Number of bits in Index ? Number of bits in Offset
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