1. Consider a computer with the following characteristics: total of 1Mbyte of main memory; Content of each addressable location is 1 byte; block size of 16 bytes; and cache size of 64 Kbytes. (a) For the main memory addresses of F0010, 01234, and CABBE, give the corresponding tag, cache line address, and word offsets for a direct-mapped cache. (b) Give any two main memory addresses with different tags that map to the same cache slot for a direct-mapped cache. (c) For the main memory addresses of F0010 and CABBE, give the corresponding tag and offset values for a fully-associative cache. (d) For the main memory addresses of F0010 and CABBE, give the corresponding tag, cache set, and offset values for a two-way set-associative cache

1. Consider a computer with the following characteristics: total of 1Mbyte of main memory; Content of each addressable location is 1 byte; block size of 16 bytes; and cache size of 64 Kbytes. (a) For the main memory addresses of F0010, 01234, and CABBE, give the corresponding tag, cache line address, and word offsets for a direct-mapped cache. (b) Give any two main memory addresses with different tags that map to the same cache slot for a direct-mapped cache. (c) For the main memory addresses of F0010 and CABBE, give the corresponding tag and offset values for a fully-associative cache. (d) For the main memory addresses of F0010 and CABBE, give the corresponding tag, cache set, and offset values for a two-way set-associative cache

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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2. Consider a computer with the following characteristics: total of 1Mbyte of main memory; Content of each addressable location is 1 byte; block size of 16 bytes; and cache size of 64 Kbytes. (a) For the main memory addresses of F0010, 01234, and CABBE, give the corresponding tag, cache line address, and word offsets for a direct-mapped cache. (b) Give any two main memory addresses with different tags that map to the same cache slot for a direct-mapped cache. (c) For the main memory addresses of F0010 and CABBE, give the corresponding tag and offset values for a fully-associative cache. (d) For the main memory addresses of F0010 and CABBE, give the corresponding tag, cache set, and offset values for a two-way set-associative cache.
1. Consider a computer wth the following characteristics: total of 1Mbyte of mainmemory; word size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes.a) For the main memory addresses of 01234 and CABBE, give the correspondingtag, cache line address, and word values for a direct-mapped cache.b) Give any two main memory addresses (based on the format identified in (a)with different tags that map to the same cache slot for a direct-mappedcache.c) For the main memory addresses of F0010 and CABBE, give the correspondingtag and offset values for a fully-associative cache.d) For the main memory addresses of F0010 and CABBE, give the correspondingtag, cache set, and offset values for a two-way set-associative cache.
Suppose a byte-addressable computer using set associative cache has 224 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache
Question 1 Consider a memory system that uses a 32-bit address at the byte level, plus a cache that uses a 64-byte line size. a)Assume a direct mapped cache with a tag field in the address of 20 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag b) Assume an associative cache. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in cache, size of tag. c) Assume a four-way set-associative cache with a tag field in the address of 9 bits. Show the address format and determine the following parameters: number of addressable units, number of blocks in main memory, number of lines in set, number of sets in cache, number of lines in cache, size of tag.
Suppose a byte-addressable computer using set associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Suppose a byte-addressable computer using set associative cache has 4Mbyes of main memory and a cache of 64 blocks, where each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache? Show all work and explain how you got the answers please. Thanks
Consider the following situation: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Based on the fact that each block has 8 bytes, figure out how big the offset field should be, and then show your work.
Let's pretend for a moment that we had a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 cache memory blocks at our disposal. Using the information that there are 8 bytes in each block, calculate the size of the offset field and show your results.
Consider a computer with the following characteristics• total of 1Mbyte of main memory• word size of 1 byte• block size of 64 bytes• cache size of 128 Kbytes.a) How many bits should be reserved for tag, line, and word offsets for a direct-mapped cache.b) How many bits should be reserved for tag and word offset for a fully-associative cache.c) How many bits should be reserved for tag, cache set, and word offset for a 8-way set-associative cache.
Consider the main memory size of 128 kB, Cache size of 16 kB, Block size of 256 B with Byte addressable memory. What is the physical address split for 2-way, 4-way and 8-way set associative?
Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?