6.7.Consider a two level memory hierarchy of the form (L1, L2) where L1 is connected directly to the CPU.Determine the average cost per bit and average access time for the data given below.Access time Hit ratio10.80.9000106Level Capacity Cost10240.1000L12160.0100L2It is necessary to transfer 512 words from a backup store to a memory section starting from address1000 and the transfer is by means of DMA. I) What are the initial values that the CPU must transfer tothe DMA controller? Give step by step account of the actions taken during the input of the first twoDWDwords.

Name: 6.7.Consider a two level memory hierarchy of the form (L1, L2) where
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Description: 6.7.Consider a two level memory hierarchy of the form (L1, L2) where L1 is connected directly to the CPU.Determine the average cost per bit and average access time for the data given below.Access time Hit ratio10.80.9000106Level Capacity Cost10240.1

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Consider a two level memory hierarchy of the form (L1, L2) where L1 is connected directly to the CPU. Determine the average cost per bit and average access time for the data given below. Level L1 L2 Capacity Cost 1024 216 0.1000 0.0100 Access time Hit ratio 10-8 0.9000 106

Consider a two level memory hierarchy of the form (L1, L2) where L1 is connected directly to the CPU. Determine the average cost per bit and average access time for the data given below. Level L1 L2 Capacity Cost 1024 216 0.1000 0.0100 Access time Hit ratio 10-8 0.9000 106

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Consider a virtual memory system that can address a total of 32 bytes. You have unlimited hard disk space, but are limited to only 16MB of semiconductor (physical) memory. Assume that virtual and physical pages are each 4 KB in size. What is the total size of the page table in bytes? (Assume that, in addition to the physical page number, each page table entry also contains some status information in the form of a valid bit (V) and a dirty bit (D)).
Let's pretend for a moment that we have a byte-addressable computer with fully associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. The following holds true if each block is 16 bits in size:a) Determine how many bytes the offset field is.Measure the tag field's width and height in pixels (b).
Suppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? c) To which cache block will the memory address 0x000063FA map?
Suppose we have a system with the following properties:The memory is byte addressable.Memory accesses are to 1-byte words (not to 4-byte words).Addresses are 12 bits wide.The cache is two-way set associative (E = 2), with a 4-byte blocksize (B = 4) and four sets (S = 4).
Answer only 3 and 4 Suppose memory has 256KB, OS use low address 20KB, there is one program sequence: (20) • Prog1 request 80KB, prog2 request 16KB, • Prog3 request 140KB • Prog1 finish, Prog3 finish; • Prog4 request 80KB, Prog5 request 120kb • Use first match and best match to deal with this sequence • (from high address when allocated) • (1)Draw allocation state when prog1,2,3 are loaded into memory? • (2)Draw allocation state when prog1, 3 finish? • (3)use these two algorithms to draw the structure of free queue after prog1 , 3 finish(draw the allocation descriptor information,) • (4) Which algorithm is suitable for this sequence ? Describe the allocation process?
Suppose a computer using direct-mapped cache has 232 (that's 232)232) bytes of byte-addressable main memory, and a cache size of 512 bytes, and each cache block contains 64 bytes. How many blocks of main memory are there? What is the format of a memory address as seen by cache, i.e. what are the sizes of the tag, block, and offset fields? To which cache block will the memory address 0x13A4498A map?
Consider a cache with the following parameters: N (associativity) = 2, b (block size) = 2 words, W (word size) = 32 bits,C (cache size) = 32 K words, A (address size) = 32 bits. You need consider only word addresses.(a) Show the tag, set, block offset, and byte offset bits of the address. State how many bits are needed for each field.(b) What is the size of all the cache tags in bits?(c) Suppose each cache block also has a valid bit (V) and a dirty bit (D). What is the size of each cache set, including data, tag, and status bits?(d) Design the cache using the building blocks in Figure 8.28 and a small number of two-input logic gates. The cache design must include tag storage, data storage, address comparison, data output selection, and any other parts you feel are relevant. Note that the multiplexer and comparator blocks may be any size (n or p bits wide, respectively), but the SRAM blocks must be 16K × 4 bits. Be sure to include a neatly labeled block diagram. You need only design the…
CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers: (a) How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate (b) Repeat the above for the index field. (c) Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.
Suppose we have a system with the following properties:The memory is byte addressable.Memory accesses are to 1-byte words (not to 4-byte words).Addresses are 13 bits wide.The cache is 4-way set associative (E = 4), with a 4-byte block size(B = 4) and eight sets (S = 8).Consider the following cache state. All addresses, tags, and valuesare given in hexadecimal format. The Index column contains the set index for each set of four lines. The Tag columns contain the tag value for each line. The V columns contain the valid bit for each line. The Bytes 0−3 columns contain the data for each line, numbered left to right starting with byte 0 on the left. A. What is the size (C) of this cache in bytes?B. The box that follows shows the format of an address (1 bit perbox). Indicate (by labeling the diagram) the fields that would beused to determine the following:CO. The cache block offsetCI. The cache set indexCT. The cache tag
) Consider the following sequence of virtual memory references (in decimal) generatedby a single program in a pure paging system:100, 110, 1400, 1700, 703, 3090, 1850, 2405, 2460, 4304, 4580, 3640a. Derive the corresponding reference string of pages (i.e. the pages the virtual addressesare located on), assuming a page size of 1024 bytes. (Assume that page numberingstarts at 0)b. For the page sequence derived above, determine the number of page faults for each ofthe following page replacement strategies, assuming that two (2) page frames areavailable to the program.i. LRUii. FIFOiii. OPT (Optimal)
Suppose a computer using fully associative cache has 4G bytes of byte-addressable main memory and a cache of 512 blocks, where each cache block contains 128 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? c) To which cache block will the memory address 0x018072 map?