Consider an instruction ADD AC, A, B which adds the contents of location A and the contents of location B into register AC, and keeps the result in AC (ACAC+ A + B). The address of A is stored in adress1 field, and the address of B is stored in adress1 field of the instruction as follows: ADD AC Address1 Address2 Write the sequence of micro-operations required for the bus structure of the following figure to perform ADD AC, A, B instruction. lines Data Internal CPU bus lines Address

Consider an instruction ADD AC, A, B which adds the contents of location A and the contents of location B into register AC, and keeps the result in AC (ACAC+ A + B). The address of A is stored in adress1 field, and the address of B is stored in adress1 field of the instruction as follows: ADD AC Address1 Address2 Write the sequence of micro-operations required for the bus structure of the following figure to perform ADD AC, A, B instruction. lines Data Internal CPU bus lines Address

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

See similar textbooks

Similar questions

If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
For example, suppose an instruction is not accepted and VA page 30 is generated. A software-managed TLB can outperform a hardware-managed TLB in the following cases:
17. Consider the following hypothetical instruction: SubMem R1, mem1, mem2 This instruction works as follows: \[ \mathrm{R} 1 \leftarrow \text { [mem1] - [mem2] } \] In a multi-cycle datapath implementation, this instruction will: a. Use the MDR twice b. Use the ALU once c. Use the "shift to left" unit twice d. None of the above Answer: B 18. Consider the following hypothetical instruction: Mems mem1, R1, mem2 This instruction works as follows: \[ \text { [mem1] } \leftarrow \mathrm{R} 1 \text { - [mem2] } \] One of the following is correct about this instruction: a. It will not need theBregister b. It will require priting into MDR twice c. It will require writing into the ALUout three times d. None of the above Answer: A 19. By comparing the hypothetical instructions given in Questions (17) and (18), if we run these instructions on the same processor, then one of the following is correct: a. Both instructions have the same CPI b. Mems executes faster than SubMem c. SubMem executes…
Consider the following register transfer statements for two 4-bit registers R1 and R2. xT: R1← R1+ R2 x' T: R1 ← R2 Every time that variable T = 1, either the content of R2 is added to the content of Rl if x = 1, or the content of R2 is transferred to R1 if x = 0. Draw a diagram showing the hardware implementation of the two statements. Use block diagrams for the two 4-bit registers, a 4-bit adder, and a quadruple 2-to-1-llne multiplexer that selects the inputs to R l . In the diagram, show how the control variables x and T select the inputs of the multiplexer and the load input of register R1.
What happens if an instruction is not accepted and it writes to VA page 30? In the following scenarios, a software-managed TLB would be faster than a hardware-managed TLB:
Suppose we have a byte-addressable memory of 20 bytes, built using 4 modules. Draw diagrams showing the distribution of addresses within each module, if we are using (a) highorder interleaving, and (b) low-order interleaving.
Consider the following fragment of C code for (i=0; i<=100; i=i+1) { a[i] = b[i] + c; } Assume that a and b are arrays of words and the base address of a is in register x17 and the base address of b is in x18. Register x19 is associated with variable i and register x20 with c. Write the code for RISC-V. How many instructions are executed during the running of the code? How many memory data references will be made during execution?
Consider the following store instruction: SW R1, 0x000F(R0). Assume that the registers R0 and R1 are initialized with 0x00000001 and 0x53A78BC Frespectively. A section of the MIPS byte addressable data memory is shown. Give the memory word of the following memory locations after the SW operation: (a). 0x00000015. (b). 0x00000014. (c). 0x00000013. (d) 0x00000012.(e). 0x00000011. (f). 0x00000010.
Registers in RISC-V are 64-bit. For the sake of simplicity, consider the following instructions operating on 32-bit registers. Assume that registers x5 and x6 hold the values 0xBBBBBBBB and 0x00000000, respectively. What is the value in x6 for the followingslli x6, x5, 6 Using the result from the part above, what is the value in x6 for the following instruction. srli x6, x6, 6
By using an equation off = ( a - b ) / [ ( d x e ) + c ];(a) illustrate the step to realize this equation by using the stack concept. (b) construct its’ CISC zero address format. (c) construct its CISC one address format. (d) construct the CISC two address format by using only 3 register. (e) In your opinion, do we need to have at least as possible instruction line? Do it will reflectthe performance of computer execution time?
What happens if VA page 30 is written even if an instruction was not accepted? An instance of a software-managed TLB would outperform a hardware-managed TLB in the following cases:
Th is exercise is intended to help you understand the relationship between forwarding, hazard detection, and ISA design. Problems in this exercise refer to the following sequence of instructions, and assume that it is executed on a 5-stage pipelined datapath:add r5,r2,r1lw r3,4(r5)lw r2,0(r2)or r3,r5,r3sw r3,0(r5)> If there is no forwarding or hazard detection, insert nops to ensure correct execution.> Repeat above step, but now use nops only when a hazard cannot be avoided by changing or rearranging these instructions. You can assume register R7 can be used to hold temporary values in your modifi ed code.> If the processor has forwarding, but we forgot to implement the hazard detection unit, what happens when this code executes?