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Course Name: Computer Architecture Branch Add Add ALU operation Data MemWrite Register # Registers Register # Address Zero PC Address Instruction ALU Data Instruction memory memory Register # RegWrite Data MemRead Control When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In a single cycle datapath where Instruction Memory (1-mem), Add, Mux, ALU, Regs, Data Memory (D-mem), and control blocks have latencies of 400ps, 100ps, 30ps, 120ps, 200ps, 350ps, and 100ps, respectively. Consider the addition of a multiplier to the ALU. This addition will add 300ps to the latency of the ALU and will add a cost of 600 to the ALU. The result will be 5% fewer instructions executed since we will no longer need to emulate the MUL instruction. What is the clock cycle time without this improvement?

Course Name: Computer Architecture Branch Add Add ALU operation Data MemWrite Register # Registers Register # Address Zero PC Address Instruction ALU Data Instruction memory memory Register # RegWrite Data MemRead Control When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In a single cycle datapath where Instruction Memory (1-mem), Add, Mux, ALU, Regs, Data Memory (D-mem), and control blocks have latencies of 400ps, 100ps, 30ps, 120ps, 200ps, 350ps, and 100ps, respectively. Consider the addition of a multiplier to the ALU. This addition will add 300ps to the latency of the ALU and will add a cost of 600 to the ALU. The result will be 5% fewer instructions executed since we will no longer need to emulate the MUL instruction. What is the clock cycle time without this improvement?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Course Name: Computer Architecture Branch Add Add ALU operation Data MemWrite Register # Registers Register # PC Address Instruction ALU Address Zero Data Instruction memory memory Register# RegWrite Data MemRead Control When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In a single cycle datapath where Instruction Memory (l-mem), Add, Mux, ALU, Regs, Data Memory (D-mem), and control blocks have latencies of 400ps, 100ps, 30ps, 120ps, 200ps, 350ps, and 100ps, respectively. Consider the addition of a multiplier to the ALU. This addition will add 300ps to the latency of the ALU and will add a cost of 600 to the ALU. The result will be 5% fewer instructions executed since we will no longer need to emulate the MUL instruction. What is the clock cycle time without this improvement?
Transcribed Image Text:Course Name: Computer Architecture Branch Add Add ALU operation Data MemWrite Register # Registers Register # PC Address Instruction ALU Address Zero Data Instruction memory memory Register# RegWrite Data MemRead Control When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In a single cycle datapath where Instruction Memory (l-mem), Add, Mux, ALU, Regs, Data Memory (D-mem), and control blocks have latencies of 400ps, 100ps, 30ps, 120ps, 200ps, 350ps, and 100ps, respectively. Consider the addition of a multiplier to the ALU. This addition will add 300ps to the latency of the ALU and will add a cost of 600 to the ALU. The result will be 5% fewer instructions executed since we will no longer need to emulate the MUL instruction. What is the clock cycle time without this improvement?
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