Table Q15 shows the micro-operations of fetch cycle, interrupt cycle, and execute cycle of the ADD instruction. Note: Accumulator (AC), internal registers (Y, Z), Interrupt Service Routine (ISR) TABLE Q15 Execute cycle of ADD instruction (i.e. ADD АС, Х) Clock cycle Fetch cycle Interrupt cycle T1 MAR PC MBR PC MAR Save address PC Memory MAR X MBR + T2 MBR Memory Memory PC – IR MBR ISR T3 MBR Y MBR T4 Z AC+ Y T5 AC Z Based on Table Q15, give the micro-operations of the execute cycle of the add instruction using the immediate addressing mode (i.e. ADIM AC, X). (a) (b) Give the micro-operations of the execute cycle of the add instruction using the indirect mode (i.e. ADIN AC, X).

20 LDA 50 21 SUB 51 50 100 51 200 Choose the contents of the registers: PC, MAR, MDR, IR, A at the end of fetch-execute cycle for instruction 20: PC MAR MDR IR A