executed because of a REP prefix, how the CPU knows when to stop?
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A: Repeat Prefix: The repeat prefixes cause repetition of sure directions that load, store, move,…
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A: Answers for both with explanation given below
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A: Required:
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A: In the given problem, we will discuss how the CPU executes a load instruction.
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A:
Q: Using the Assembly Language Programming of 8086, write and simulate a program that adds two data…
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A: Given: A program accesses ten continuous memory locations. The CPU will take less time if the…
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A: Answer)
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A: Assembly code as,
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A: Please find the answer below:
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A: Answer:
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A:
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A: Given: ASSEMBLY Local variables are stored on the runtime stack, at a higher address than the…
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A: Solution: #Assembly code: reverse: push rbp mov rbp, rsp mov DWORD PTR [rbp-20], edi mov DWORD…
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A: Answer is given below-
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- Copy the top 2 words from the stack into registers AX and CX respectively. Do this withoutchanging the stack pointer do not use POP instructions! Use BP as the base register. Howwill your program know what value to place in BP?To ensure that the stack contains some known values, place the following code at thebeginning of your program:mov dx, 1234Hpush dxmov dx, 0ABCDHpush dxSave the based.s source file as /home/username/project1/based.sPlease answer the following with the reference; 1a. What is the purpose of the movq 0x10 (%rdi), rbp instruction here (at the C level or higher)? How does this relate to the earlier call to pushq rbp? 1b. Alice just remembered that the original C code had the following structure! Using what you now know about mystery, fill in the blanks with C code. long mystery ( TreeNode* t){ If ( ) { return ; } return }Question1: Multiple Choice : (please leave it to other tutors who can answer all my sub-question since this is my last question for this month) 1-If for some inputs, a procedure never terminates, the procedure lacks a. computability b. definiteness c. finiteness d. scalability 2-The elements of the ISA for a particular type of CPU include a. addressing modes b. data types c. instructions d. a and b e. a, b and c Question 2: Perform the following logical operations and express your answers in hexadecimal notation. x3487 AND x7254 xABCD or x3234 xF098 XOR x3344
- 25: . Find the time delay in the following program if the crystal frequency is 1 MHz. Do not ignore the time delay due to the first and last instruction. DELAY: LDI R16, 30 AGAIN: LDI R17, 35 HERE: NOP NOP DEC R17 BRNE HERE DEC R16 BRNE AGAIN RET 26: Write a program to display 2 on 7 segment. A 7 segment is connected to PortD.Consider the following instruction:Instruction: Add Rd, Rs, RtInterperation: Reg[Rd] = Reg[Rs] + Reg[Rt] RegWrite MemRead ALUMux MemWrite ALUOp RegMux Branch a, What are the values of control signals generated by the control in Figure 4.2 for the above instruction? b, Which resources (blocks) perform a useful function for this instruction? c, Which resources (blocks) produce outputs, but their outputs are not used for this instruction? d, which resources (blocks) produce no output for this instruction?When we execute a program that contains a lot of if-statements or for/while-loops, the pipelineof Teletraan-2 faces a problem. The instruction fetch stage does not know which branch of theif-statement shall be fetched, until the write back stage writes the True/False value of the ifcondition to a flag register. What should we do to alleviate the problem?A. Don't wait. Let the CPU predict which branch will probably be executed, and fetch theinstruction(s) of that branch. If it is later revealed the prediction is wrong, undo theinstruction(s).B. Don't wait. Fetch-decode-execute the instructions of all branches of the if-statement.C. Nothing. We can only let the instruction fetch stage wait for the write back stage to finishwriting the value of the if-condition.D. Eliminate all if-statements during the assembly process.
- Write MIPS assembly for the following function. Assume N is passed to yourfunction in register $a0. Your output should be in register $v0 at the end of yourfunction. Note: You must implement this function recursively. The purpose of thisassignment is to learn how to manipulate the stack correctly in MIPS. int Myfun (int N){ if (N<3) return 1; return ( 2* Myfun(N-1)+ Myfun(N-2));}Please explain each instruction with a comment. Please submit your source codeand a screenshot that shows the registers with correct output value for N=3, i.e.,Myfun(3) returns 3 and Myfun(4) returns 7For the (pseudo) assembly code below, replace X, Y, P, and Q with thesmallest set of instructions to save/restore values on the stack and update the stackpointer. Assume that procA and procB were written independently by two differentprogrammers who are following the MIPS guidelines for caller-saved and callee-savedregisters. In other words, the two programmers agree on the input arguments andreturn value of procB, but they can't see the code written by the other person. procA:$s0 = ...$s1 = ...$s2 = ...$t0 = ...$t1 = ...$t2 = ...X$a0 = ...$a1 = ...jal procBY... = $s1... = $t0... = $t1... = $a0jr $raprocB:P... = $a0... = $a1$s2 = ...$t0 = ...Qjr $raAdd control states to the following to implement a bitwise-OR-with-immediate instruction (as decoded by the when below), such that ori $rt,$rs,immed yields rt=(rs|immed). This is actually a MIPS instruction, as we'll discuss later. Hint: except for using bitwise OR instead of addition, it's essentially the same as the addi that is already handled by: when (op()) {addi} Addiwhen (op()) {ori} OriStart: PCout, MARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRout, IRin Zout, PCin, JUMPonop HALT /* Should end here on undecoded op */Addi: SELrs, REGout, Yin IRimmedout, ALUadd, Zin Zout, SELrt, REGin, JUMP(Start)Ori: You can test your specification using the http://super.ece.engr.uky.edu:8088/cgi-bin/simple.cgiLinks to an external site. simulator. For testing, you can add the initial conditions: MEM[0]={ori}+rs(9)+rt(10)+immed(3)MEM[4]=0$9=5 Register $10 should end-up holding the value 0x00000007 (3|5 = 7 decimal).
- Add control states to the following to implement a bitwise-OR-with-immediate instruction (as decoded by the when below), such that ori $rt,$rs,immed yields rt=(rs|immed). This is actually a MIPS instruction, as we'll discuss later. Hint: except for using bitwise OR instead of addition, it's essentially the same as the addi that is already handled by: when (op()) {addi} Addiwhen (op()) {ori} OriStart: PCout, MARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRout, IRin Zout, PCin, JUMPonop HALT /* Should end here on undecoded op */Addi: SELrs, REGout, Yin IRimmedout, ALUadd, Zin Zout, SELrt, REGin, JUMP(Start)Ori: You can test your specification using the http://super.ece.engr.uky.edu:8088/cgi-bin/simple.cgi (Links to an external site.) simulator. For testing, you can add the initial conditions: MEM[0]={ori}+rs(9)+rt(10)+immed(3)MEM[4]=0$9=5 Register $10 should end-up holding the value 0x00000007 (3|5 = 7 decimal).Implement a new unary instruction in place of N0P0 called ASL2 that does two left shifts on the accumulator. V should remain unchanged, but N and Z should correlate with the new value in the accumulator, and C should be the carry from the second shift. Write a program that tests all the features of the new instruction.Write and simulate a MIPS assembly-language routine that: 1. Prints your group number, for example “Group 1”, 2. Computes the dot product of two vectors, A_vec and B_vec, as described in Lab 4 of the Lab Manual, 3. Stores the result at memory word DOTPROD, and 4. Prints the result preceded by the phrase: “The result of the dot product is: “. Your data segment should look like the following: .data group: .asciiz “\nGroup x” msg: .asciiz "\nThe result of the dot product is: " A_vec: .word x, 4, 20, 13, 3, 10, 5 B_vec: .word 4, 2, 1, 2, 5, 2, 4 n: .word 7 DOTPROD: .word 0 Replace each “x” with your group number.