Figure Q4(a)(1) shows two unit of multiple clock source. Referring to the internal circuit diagram of this IC shown in Figure Q4(a)(ii), obtain the frequency at f1, f; and f3. (4-bit binary counter) configured to generate f2 fa fi 1 (10) CP (8) (10) CP (8) Q4 100H2- Q4 (11) CP (4) Q2 (11) CP (4) Q2 (5) Q! (9) QO (5) Q! (12) MR, & (12) MR, & (9) QO (13) MR (13) MR; Figure Q4(a)(i) 2.

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ChapterS: Safety, Basic Electricity And Ohm's Law
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digital electronics

Q4 (a) Figure Q4(a)(i) shows two unit of 74LS293 (4-bit binary counter) configured to generate
multiple clock source. Referring to the internal circuit diagram of this IC shown in Figure
Q4(a)(ii), obtain the frequency at fi, f2 and f3.
f1
f2
f3
1
2
(10)
CP
(8)
(10)
(8)
CP.
100HZ-
(11)
CP
(4)
Q2
(11)
CP
(4)
Q2
(5)
(5)
Q1
Q!
(12)
MR,
&
(9)
QO
(12)
MR,
&
(9)
QO
(13)
MR
(13)
MR
Figure Q4(a)(i)
Transcribed Image Text:Q4 (a) Figure Q4(a)(i) shows two unit of 74LS293 (4-bit binary counter) configured to generate multiple clock source. Referring to the internal circuit diagram of this IC shown in Figure Q4(a)(ii), obtain the frequency at fi, f2 and f3. f1 f2 f3 1 2 (10) CP (8) (10) (8) CP. 100HZ- (11) CP (4) Q2 (11) CP (4) Q2 (5) (5) Q1 Q! (12) MR, & (9) QO (12) MR, & (9) QO (13) MR (13) MR Figure Q4(a)(i)
1
PRE
PRE
PRE
PRE
J
J
J
Q
CP.
K
K
K
K
CLR
CLR
CLR
CLR
CP,
MR,-
MR2
Q2
Qo
Q1
Q3
Figure Q4(a)(ii)
Transcribed Image Text:1 PRE PRE PRE PRE J J J Q CP. K K K K CLR CLR CLR CLR CP, MR,- MR2 Q2 Qo Q1 Q3 Figure Q4(a)(ii)
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