Here is the question about mips.Q1). Suppose $s0 stores the base address of word array A and $t0 is associated with m, convert the following instruction into MIPS. A[240] = A[240+m]Q2). Suppose $t0 stores the base address of word array A and $s0 is associated with m, convert the following instruction into MIPS. m= 0 while (m <= 10): A[m] = A[m+4]*6 m = m + 6
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Here is the question about mips.
Q1). Suppose $s0 stores the base address of word array A and $t0 is associated with m, convert the following instruction into MIPS.
A[240] = A[240+m]
Q2).
Suppose $t0 stores the base address of word array A and $s0 is associated with m, convert the following instruction into MIPS.
m= 0
while (m <= 10):
A[m] = A[m+4]*6
m = m + 6
Step by step
Solved in 1 steps
- dont use ai to do it !!! Q1). Suppose $s0 stores the base address of word array A and $t0 is associated with m, convert the following instruction into MIPS. A[240] = A[240+m]Q2). Suppose $t0 stores the base address of word array A and $s0 is associated with m, convert the following instruction into MIPS. m= 0 while (m <= 10): A[m] = A[m+4]*6 m = m + 5We will explore the impact of cache capacity on performance, focusing exclusively on the data cache and excluding instruction storage in the caches. Cache access time is directly linked to its capacity. For the sake of simplicity, let's assume that accessing the main memory takes 100ns, and in a specific program, 50% of instructions involve data access. Two distinct processors, denoted as P1 and P2, are engaged in executing this program. Each processor is equipped with its own L1 cache. L1 size L1 Miss Rate L1 Hit Time P1 64 KB 3.6% 1.26 ns P2 128 KB 3.1% 2.17ns (a) What is the AMAT for P1 and P2 assuming no other levels of cache?Consider a multilevel computer in which levels are vertically stacked, with the lowest level being level 1. Each level has instructions that are m times as powerful as those of the level below it; that is, one level r instruction can do the work of m instructions at level r-1. However, n instructions at level r-1 are required to interpret each instruction at level r. Given this, answer the following questions: If a level 1 program requires k seconds to run, how long would the equivalent program take to run at levels 2, 3 and 4. Express your answer in terms of n, m, and r. What is the performance implication for the program if n > m? Conversely, what is the implication if m > n? Which case do you think more likely? Why?
- This problem is adapted from an earlier edition of P&H, and should be submitted.Consider the following code used to implement a new instruction: foo $t3,$t1,$t2:mask : . word 0xFFFFF83Fs t a r t : l a $t0 , masklw $t0 , 0 ( $ t 0 )l a $t3 , s h f t rlw $t3 , 0 ( $ t 3 )and $t3 , $t3 , $ t 0a ndi $t2 , $t2 , 0 x 0 0 1 fs l l $t2 , $t2 , 6o r $t3 , $t3 , $ t 2l a $t5 , s h f t rsw $t3 , 0 ( $ t 5 )s h f t r : s l l $t3 , $t1 , 0Add meaningful comments to the code and write a brief (2 sentence max) description of what foo does. Thisis not the same as saying how it does it - e.g., when asked to describe what a pedestrian is doing, you wouldsay they are walking, not that they are ilfting their left leg, angling it forward, putting it down, . . ..State at least one reason why writing “self-modifying code” such as this is a bad idea (and often times notactually allowed by the operating system)?Consider the following instruction:Instruction: Add Rd, Rs, RtInterperation: Reg[Rd] = Reg[Rs] + Reg[Rt] RegWrite MemRead ALUMux MemWrite ALUOp RegMux Branch a, What are the values of control signals generated by the control in Figure 4.2 for the above instruction? b, Which resources (blocks) perform a useful function for this instruction? c, Which resources (blocks) produce outputs, but their outputs are not used for this instruction? d, which resources (blocks) produce no output for this instruction?Q1). Suppose $s0 stores the base address of word array A and $t0 is associated with m, convert the following instruction into MIPS. A[240] = A[240+m]Q2). Suppose $t0 stores the base address of word array A and $s0 is associated with m, convert the following instruction into MIPS. m= 0 while (m <= 10): A[m] = A[m+4]*6 m = m + 5
- Consider a 32-bit computer with the MIPS assembly set, that executes the following code fragment loaded in memory in the address 0x0000000. li $t0, 1000 li $t1, 0 li $t2, 0 loop: addi $t1, $t1, 1 addi $t2, $t2, 4 beq $t1, $t0, loop This computer has a 4-way associative cache memory of 32 KB and lines of 16 bytes. Calculate the number of cache miss of the previous code, and the hit ratio, assuming that no other program is executing and that the cache memory is initially empty.Please answer the following; a. What registers are implicitly changed by an x86 call instruction in what way? b. Write an x86 assembly code to implement the following function based on known array offsets. An optimal solution is 3 lines of assembly including the return. //add two specific elements int f(int a[a][2]){ return a[0] [1] + a[2] [1]; }Consider the code sequence below lw $t1, 4($t0) add $s2, $t1, $t2 lw $t3, 16($t0) add $s3, $t3, $t2 lw $t4, 28($t0) add $s4, $t4, $t2 Suppose there is no forwarding allowed, and for the result of a lw to be consumed by the following R-type of instruction requires 2 bubbles to be placed between the two instructions. Is it possible for the scheduler to juxtapose the commands in such a way that there is no need for any bubbles? If yes, give an example of how it can be done.
- Assume you now have 1kB of memory, i.e. the memory address space runs from 0 to 1023. The starting address of the first word is 0, the second word is 4, the third word is 8, and so on. The last word comprising 4 bytes resides in addresses 1020, 1021, 1022, 1023. Thus, the last word starts at 1020, which is a multiple of 4. Now assume the same 1kB of memory but now, word size is 64 bits. The starting address of the first word is 0, the second, third, and last word starts at? my answer: (correct) the second is equal to = 8 the third is equal to = 16 help me find the last wordAssume you now have 1kB of memory, i.e. the memory address space runs from 0 to 1023. The starting address of the first word is 0, the second word is 4, the third word is 8, and so on. The last word comprising 4 bytes resides in addresses 1020, 1021, 1022, 1023. Thus, the last word starts at 1020, which is a multiple of 4. Now assume the same 1kB of memory but now, word size is 64 bits. The starting address of the first word is 0, the second, third, and last word starts at?Assume (hypothetically) that there is a version of QtSpim that simulates a 4-core processor. Write a MIPS Assembly program that would take advantage of the 4 cores to speed up the execution of mathematical calculations. Specifically, write a program that receives as input two arrays of equal length, and replaces the content of each element in Array 1 with the sum of the corresponding elements in Array 1 and 2.