Part 5: You have to design a logic diagram which can implement the complement of following by using NAND gates ONLY. F (A, B, C, D) = Σ (0, 1, 2, 3, 6, 10, 11, 14) ALL FIGURES ARE GIVEN IN PICTURES
USE DIGITAL LOGIC AND DESIGN
Part 1: In Figure_4; we have 4-bit Comparator using 2-bit Comparators block. You have to satisfy given condition by applying all data on figure 4. At the end, given condition should produce HIGH output and other two should be LOW.
A3 A2 A1 A0 = 1101 and B3 B2 B1 B0 = 1110
Figure_4
Part 2: The serial data-input waveform (Data in) and data-select inputs (S0 and S1) are shown in Figure_5. Determine the data-output waveforms from D0 through D3.
Figure_5
Part 3: Decoder can be useful when we have to decode some specific numbers from their equivalent code. Figure 6 has a concept of 3 to 8 line decoder from which you have to generate output waveform from D0 to D7 with proper relationship to input.
Figure_6
Part 4: The data-input and data-select waveforms in Figure 7 are applied to the multiplexer. Determine the output waveform F in relation to the inputs.
Figure_7
Part 5: You have to design a logic diagram which can implement the complement of following by using NAND gates ONLY.
F (A, B, C, D) = Σ (0, 1, 2, 3, 6, 10, 11, 14)
ALL FIGURES ARE GIVEN IN PICTURES
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