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- Based on your perspective, briefly discuss the structure of the different types of binary codes. What are the differences between asynchronous and synchronous sequential logic circuits? Rationalize your answer. Design a simple logic circuit for a Set/Reset (SR) Latch, based on any actual application of latches. Describe your design using at least three (3) sentences. Give three (3) applications of Flip-flops, and describe the process of each.1. Obtain a logic data book and list down all the available multiplexers, decoders, and decoder/demultiplexers. 2. Show how 74251 8-to-1 line multiplexers may be connected to implement a 16-to-1 MUX. 3. What are the advantages and disadvantages of the MUX and the decoder methods over one another? 4. Describe how a combinational circuit may be implemented using decoders given the minterm list form of two functions. 5. What are the advantages and disadvantages of the MUX and the decoder methods over conventional methods of implementing a function using logic gates?5 (b)How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates? Also draw the circuit.
- First, you must create a logic circuit using only basic gates such as AND, OR, NOR, NAND, NOT, etc. to implement an ADDER capable of adding two 4 bit binary numbers. Second, you must create a logic circuit using only basic gates such as AND, OR, NOR, NAND, NOT, etc. to implement a Subtractor that is capable of subtracting the second number from the first, by converting the second number into its 2's complement form and then adding the resulting number to the first number. You do not need to worry about accomodating the addition or subtraction of negative numbers. Finally, create a limited ALU (Arithmetic logic unit) circuit using Logism that implements a Full Adder circuit capable of adding 2 – 4 bit binary numbers and subtracting 2- 4 bit binary numbers. Also, implement the ability to select a bitwise AND operation and a bitwise OR operation. For the ALU it is acceptable to use the Adder and Subtractor circuits that are listed under the "Arithmetic" folder in Logism. (Logism tips and…1. Draw a circuit to get mod-12 counter?What is the modulus if Q3 and Q0 drive the nand gate?A multiplier is to be designed for two 2-bit inputs using the algorithm. (Draw schematic, truth table, and write Verilog HDL code) (Use: and, not, xor gates)A result will be written at 7-segment on the Altera FPGA board. (Draw schematic, truth table) (Use: and, or, not, xor gates)
- 3(a): Consider the following circuit, which uses two D flip-flops with falling edge triggers along with -bit full adder. The flip-flops are controlled by a single clock, C. Suppose C, Q0 and Q1 all initially have the value 0. First, fill in the blanks in the "i " = 0 (initial state)" row to show the values of D0 and D1 at this initial time (assume the results of the adder have had time to stabilize) . Next, show the values of Q0 , Q1, D0 , and D1 once they have stabilized after the ith falling edge of the clock, where i ranges from 1 to 4. Note that both the A and Carry In inputs of the adder are (Q not ) Q'0 not Q0 None of these first four rows should be the exactly the same.Design a two-bit counter (sequential circuit) using falling edge triggered T-flipflops, with one input line x. When x= 1, the state of the circuit remains the same. When x = 0, the circuit goes through the state transitions byincrementing the state count, i.e., from 00 to 01, 01 to 10, 10 to 11, and 11 to 00, and repeats. Draw circuit diagramof the designed counter. if z=83,Convert z to Base-2, e.g., z= (156)10 = (10011100)2.Provide this bitstream as input to K and draw the timing diagram of the outputs of both the T-flipflops.Generate a 2-bit up counter (C1C0) with output S = 1 if d1d0 > C1C0 and S = 0 if d1d2 <= C1C0.a) Design the 2-bit counter circuit that cycles C1C0 = 00, 01, 10, 11 and loops back to 00, with inputsd1d0 and output S. Show the state transition tableb) Show the state machine diagramc) Derive the logical functional expressions, and logic circuitd) Draw the timing diagrams for S for both 25% and 75% duty cycles. At minimum, these should havethe CLK for the 2-bit counter, C1, C0 and S i created table, but I am not sure if it is correct.
- 5) Assume that the exclusive-OR gate has a propagation delay of 10 ns and that the AND or OR gates have a propagation delay of 5 ns. What is the total propagation delay time in the four-bit adder of the below circuit?Draw a circuit that implements a 3-bit Adder that takes two 3-bit numbers as input, each on 3 input lines and outputs a 4 bit number on 4 output lines. You may use the Half Adder, the Full Adder and the following gates: NOT, AND, OR, XOR. Make sure to clearly label the interface wires on your diagram and the types of gates you use.Using 4 exclusive –Or gates and a 4-bit full adder MSI circuit, Construct a 4- bit paralle3l adder/ Subtractor. Use a select input variable V so V=0 the circuit adds and when v=1, the circuit subtracts.