Problem #2: A synchronous counter counts up to 211. a) What is the MOD number of this counter? b) How many J-K FFs will be required to design this counter?
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- What is an MSDS?A 9 bit asynchronous counter has a 128 - kHz clock signal applied. i) What the mod Number of this counter ? ii) What will be the frequency at the MSB output ? iii) Assume that the counter starts at zero.What will be the count after 6.15 input pulse?A)What will be the frequency at C if the clock is 320 kHz? B) What is the modulo of the circuit? C) What is the output (in binary) after 737 pulses?
- A 16-bit successive approximation ADC is to be designed to operate at 50,000 conversions/second. What is the clock frequency? How rapidly mustthe unknown and reference voltage switches change state if the switch timing delay is to be equivalent to less than 0.1 LSB time?Explain each component of the block diagram of a frequency counter. - Input: - Accurate time-base / clock: - Decade dividers and flip-flop: - Gate: - Counter/ latch: - Display:(a) How many FFs are required to build a binary counter that counts from 0 to 1023?(b) Determine the frequency at the output of the last FF of this counter for an input clock frequency of 2 MHz.(c) What is the counter’s MOD number?(d) If the counter is initially at zero, what count will it hold after 2060 pulses?
- S Display will be designed for a thermometer. The display will show that degree for minimum temperature and 99 degrees for maximum temperature. According to this; a) What is the number of bits that will be needed in the binary code to express the temperature? b) What are the binary, octal and hexadecimal equivalents of 95 degrees? () What is the BCD representation of 95 degrees? d) What is the hex equivalent of this temperature when it shows 111 degrees octal? e) If the thermometer showed a temperature between -99 and +99 degrees, how many bits would we need?Sketch a timing diagram of a 4-bit binary counter like the 74X163 showing the clock signal CLK and the states Q3Q2Q1Q1 as it counts from 0 to 15. What is the frequency of Q3 compared to that of the CLK?Draw the Moore and Mealy State Diagram of a Finite State Machine thatfunctions as a Binary Sequence Detector for the following sequence:a. 01011b. 101 and/or 010Obtain the State Table for each of your diagrams?
- The initial state of the four-bit synchronous binary addition counter Q3Q2Q1Q0 is 1100. After 8 CP clock pulses, its state Q3Q2Q1Q0 changes to ----?Design a three bit synchronous binary counter that counts two by two with T-flipflops,continously. Output should be one when the counter equals maximum number.a. Draw the exitation table b. Draw the corresponding state diagram. c. Tabulate the state table for the sequential circuit. d. Draw the logic diagram of the circuit.2.Assuming the processor frequency is 20 MHz, find the highest square wave frequency that can be generated using Timer0 in 16-bit mode. (Calculations only, no code needed).