Problem 3 ( Parallelizable programs are typically accelerated by a factor of 100 on a GPU with 2,000 cores. What percentage of the total execution time (on a single core) of such programs is allocated to sequential parts of the program and what percentage of time is allocated to parallelizable parts of the program? Explain your steps clearly.

Problem 3 ( Parallelizable programs are typically accelerated by a factor of 100 on a GPU with 2,000 cores. What percentage of the total execution time (on a single core) of such programs is allocated to sequential parts of the program and what percentage of time is allocated to parallelizable parts of the program? Explain your steps clearly.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?
1. When a program is adapted to run on multiple cores in a multiprocessor system, the execution time on each core is comprised of computing time and the overhead time required for locked critical sections and/or to send data from one core to another. Assume a program requires t = 200 sec of execution time on one core. When run on n cores, each core requires t/n sec, as well as an additional 10 sec of overhead, irrespective of the number of cores. a. Compute the per-core execution time for 2, 4, 8, 16, 32, 64, and 128 cores. b. For each case, list the corresponding speedup relative to a single core and the ratio between actual speedup versus ideal speedup (speedup if there was no overhead).
headwriting 1 4. Which is the speedup that can be obtained on 100 processors if 93% of the program is ideally parallel, the remaining part is sequential and the sequential execution time is 10000 s?
Question 3. A program is executed for 1 sec, on a processor with a clock cycle of 50 nsec and Throughput₁ = 10 MIPS. 1. How much is the CPI1, for the program? 2. Let us assume that, thanks to the introduction of a superscalar processor, the throughput of the program is optimized. In the new case, the 50% of the program instructions is executed with 3 parallel issues, while the fraction of remaining instructions (50%) is executed with one issue. a. How much is the Speedup from the case (1) to the case (2)? b. How much is the Throughput2 expressed in MIPS?
(d) A process wishes to transfer to main memory n bytes of data from an I/O device which can internally buffer up to b (b
Problem: In a certain computer system, five (5) processes A, B, C, D, and E are active with their burst times (in ms) of 8, 10, 2, 4, and 3 respectively. These processes come at times (in ms.) 16, 0, 4, 20, and 29 respectively and use FCFS to schedule the execution. Required information: Draw the Gantt chart showing the execution of the CPU. What is the CPU utilization? What is the system’s throughput (in process /ms)?
5. Consider two microprocessors having 8- and 16-bit-wide external data buses, respectively. The two processors are identical otherwise and their bus cycles take just as long. (a) Suppose all instructions and operands are one byte long, by what factor do the maximum data transfer rates differ?
Question 24 Given a CPU with 24-bits address bus and multiple blocks of 1MB memory units. It is required to design a main memory system that maximizes the main memory size but without using any extra hardware. A) What is the maximum blocks of 1MB memory units that can be used? B) What is the main memory size that can be acheived? C) What is the memory decoding technique that can be used? D) Draw the block diagram that shows the system design. In your diagram, show clearly the connections between the CPU address lines (A23-AO) and the individual 1MB memory blocks. The system CPU can access the memory by activating M/(IOJ and R/W control signals. Address Lines D7-Do Address Bus RW CPU D7-Do IMBRAM CSI MIO RW Cs2 CS1 Memory Function Write Operation Read Operation Memory Block is not elected Memory Block is not selected CS2 R/W 1 1 1 1 X. X X X
Assume that the operation times of one add instruction for the major functional units are 325 ps for memory access, 185 ps for ALU operations and 125 ps for register file read/writes. Please fill the table first and perform the following a )What is the total cycle in single-cycle implementation? b )What is the total cycle in pipelining implementation? c) What is the total cycle in pipelining implementation if there are 5 million add instructions? d) What is the total cycle in pipelining implementation for 5 million add instructions, if the stages are balanced? e)What is the speed up of pipelining implementation over single-cycle implementation?
2. Suppose we have two implementations of the same instruction set architecture. Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some program and computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the same program. Which computer is faster for this program and by how much?
(i) Assume the processor is driven by a clock, such that each control step is 4 ns in duration. How long will the processor have to wait during memory read operation assuming that a memory read operation takes 12 ns to complete? What percentage of time is the processor idle during execution of the above instruction in single bus organization?
a. what is the clock cycle time in a pipelined and non-pipelined processor? b. what is the total latency of an LW instruction in a pipelined and non-pipelined processor? c. If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split, and what is the new clock cycle time of the processor?