Q-4. On a system using simple segmentation, compute the physical address for each of the logical addresses, given the following segment table. If the address generates a segment fault, indicate this as well. Segment Base Length 124 330 1 876 211 111 99 3 498 302 (a). 0, 99 [Segment#, Offset] Ans = (b). 2, 78 Ans = (c). 1, 265 Ans =

Q-4. On a system using simple segmentation, compute the physical address for each of the logical addresses, given the following segment table. If the address generates a segment fault, indicate this as well. Segment Base Length 124 330 1 876 211 111 99 3 498 302 (a). 0, 99 [Segment#, Offset] Ans = (b). 2, 78 Ans = (c). 1, 265 Ans =

Name: Don't copy paste. Give me correct one and unique answer Q-4. On a syst
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Description: Don't copy paste. Give me correct one and unique answer Q-4. On a system using simple segmentation, compute the physical addressfor each of the logical addresses, given the following segment table. If theaddress generates a segment fault, indicate th

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Assume the following parameters for Go-Back-N: a) N = 4b) Round Trip Time (RTT) = 10 msc) Timeout period = 40 msd) Segment Size = 1700 bytesSuppose that Bob sent 10 data segments, numbered 1 through 10, to Aliceusing the Go-Back-N mechanism. Suppose that data segment 4 and datasegment 8 were lost the first time the segments were sent to Alice (butreached Alice correctly when retransmitted). There were no other segmentlosses apart from the aforementioned. What is the average throughputobtained in sending all the data segments (in bytes/sec)? Draw a diagramto show the communication process in detail.
A computer with 32 bits virtual address uses a two-level page table. Virtual addresses are split into a 10 bits top-level page table field (PT1), a 10 bits second-level page table field (PT2), and an offset. How many PT1, PT2, and offset with virtual address 0x00403008? A. PT1=1; PT2=1; offset=8B. PT1=1; PT2=3; offset=8C. PT1=4; PT2=3; offset=8D. PT1=4; PT2=1; offset=8
a) In the SRAM region, what is the corresponding bit-band alias address for the bit [4] of the memory address of 0 * 2000008 b) In the Peripheral region, if the value in the alias address 0 * 4200 0088 to 0 * 4200 008B was set to 0x00000001, what is the bit # and the address in the peripheral region that wants to set to 1?
Suppose we have a byte-addressable computer using direct mapping with 16-bit main memory addresses and 32 blocks of cache. If each block contains 8 bytes. a. Determine the number of bits of the tag field. b. To which cache block would the hexadecimal address 0x2468 map? c. What is the tag of the hexadecimal address 0x2468
c. Given a standard memory size of 215block, briefly explain how many addressable locations can beaccessed by an SIC machine and why
Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. 8 bits are used for offset, 8 bits are used for page # and the max number of pages a process can have is 256. e. Translate the following virtual addresses to physical addresses, and show how you obtain the answers. (Hint: You do not need to convert hexadecimal numbers to decimal ones.) 0x0389 0xDF78 0x0245 0x8012 f) Now, suppose that the OS uses a two-level page table. Draw the page table. (Assume that frames 7 through 221 are free, so you can allocate space for the page table there.) In addition, suppose that the page-table directory storage comprises a whole number of consecutive full frames. (For examples: if the directory entry is 2 bytes, the entry’s storage comprises 1 frame; if the directory entry is 260 bytes, the entry’s storage comprises 2 consecutive frames.) g)What is the size of the two-level page table…
Determine the number of page table entries (PTEs) that areneeded for the following combinations of virtual address size(n) and page size (P):
Consider the following segment table (all expressed and addressed in bytes) Segment Base Length 0 500 1000 1 4500 1500 2 7000 3000 3 11000 2400 4 15000 875 What are the physical addresses for the following logical addresses? a. 0,430 b. 1,1520 c. 2,500 d. 3,400 e. 4,1120
For a microprocessor the code segment starts at 20000H, and stack segment starts at 21000H.Physical addresses from 21000H to 2FFFFH are accessible from both code and stack segment.These are the physical addresses.● If a location has CS: IP=2000H: 3000H, can we access this location with SS: SP? If yes,what is the SS: SP for this location? If no, why is it not accessible?● If another location has CS: IP=2000H: 0030H, can we access this location with SS: SP? Ifyes, what is the SS: SP for this location? If no, why is it not accessible?
Suppose, 3BD15 H is a particular physical location, and 1234 is the value of the offset.What should be the base address of the segment? Will there be any problems with thisbase address? give the calculation Suppose CS = 1000H, DS = 2000H, ES = 3000H, SS = 4000H and SI = 1234H. In thiscase what is the physical address generated as the source in the given command:“ mov ax, [si] ”
In an architecture with 18 bits of "virtual address" width, "page size" is given as 1024 bytes and "physical address" width is given as 15 bits. TLB has a “2-way set associative” structure and contains a total of 16 data blocks. What is the TLB Tag field width in this architecture? A) 4 B) 5 C) 6 D) 7 E) 8
4. Given that the main memory size is 32KB, the page size is 64B, the word size is 1B, and n-level paging is applied. What is the page number size? If (5, 10) is a record in the outer page table stored in PCB and (9, 7) is a record in the inter page table stored in page frame No.10, what is the physical address of the logical address 0010101001000110 in HEX?