Q: For a basic computer that is currently running in its timing TO of execution for an instruction that is located in memory location 366. The content of AC is (212) and the content of memory locations are as follow: [memory location: content]: [365:9473], [366:7010], [367:5431], [368:4620], [431:1A23], [620:C80D]. Answer the following questions that examine the contents of PC, AR, AC, DR and IR after the end of execution for the next instruction. (Note: all numbers are in

Q: For a basic computer that is currently running in its timing TO of execution for an instruction that is located in memory location 366. The content of AC is (212) and the content of memory locations are as follow: [memory location: content]: [365:9473], [366:7010], [367:5431], [368:4620], [431:1A23], [620:C80D]. Answer the following questions that examine the contents of PC, AR, AC, DR and IR after the end of execution for the next instruction. (Note: all numbers are in

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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(Practice) Although the total number of bytes varies from computer to computer, memory sizes of millions and billions of bytes are common. In computer language, the letter M representsthe number 1,048,576, which is 2 raised to the 20th power, and G represents 1,073,741,824, which is 2 raised to the 30th power. Therefore, a memory size of 4 MB is really 4 times 1,048,576 (4,194,304 bytes), and a memory size of 2 GB is really 2 times 1,073,741,824 (2,147,483,648 bytes). Using this information, calculate the actual number of bytes in the following: a. A memory containing 512 MB b. A memory consisting of 512 MB words, where each word consists of 2 bytes c. A memory consisting of 512 MB words, where each word consists of 4 bytes d. A thumb drive that specifies 2 GB e. A disk that specifies 4 GB f. A disk that specifies 8 GB
Consider a machine with three instruction classes and CPI measurements as follows: Instruction class CPI of the instruction class A 2 B 5 C 7 Suppose that we measured the code for a given program in two different compilers and obtained the following data: Code sequence Instruction counts (in millions) A B C 1 15 5 3 2 25 2 2 Assume that the machine’s clock rate is 500 MHz. Which code sequence will execute faster according to MIPS? How much according to execution time of each code sequence?
Consider a multilevel computer in which levels are vertically stacked, with the lowest level being level 1. Each level has instructions that are m times as powerful as those of the level below it; that is, one level r instruction can do the work of m instructions at level r-1. However, n instructions at level r-1 are required to interpret each instruction at level r. Given this, answer the following questions: If a level 1 program requires k seconds to run, how long would the equivalent program take to run at levels 2, 3 and 4. Express your answer in terms of n, m, and r. What is the performance implication for the program if n > m? Conversely, what is the implication if m > n? Which case do you think more likely? Why?
Suppose the implementation of an instruction set architecture uses three classes of instructions, which are called A, B, and C. The total dynamic instruction count is 1 x 10^7 and the processor's clock rate is 2.5 GHz. Details for the three classes are given in the table below: Class CPI % of instructions A 1 20% 50% C 3 30% Complete the following table. Express all answers in scientific notation and round to two decimal places, when needed. Class Instruction Count Number of Clock Cycles х 10^ x 10^ A х 10^ х 10^ x 10^ х 10^ C
In this exercise, we examine in detail how much an instruction is executed in a single-cycle Datapath. The problem refers to a clock cycle in which the processor fetches the following instruction word: 1010 1100 0110 0010 0000 0000 0001 0100. Assume that data memory is all zeros and that the processor's registers have the following values at the beginning of the cycle in which of the instruction word is fetched: (See image attached) What is the new PC address after this instruction is executed? Highlight the path through which this value is determined?
Assume that a personal computer must get FIVE pieces of data from itsmemory for every operation (one piece of data indicates Which instructionto perform: the other is the intormation which is operated on). If thecomputer is the size of a typical PC. how long does it take to get these pieceof data? From this, what is the maximum rate at which the PC can executeuctions?
Consider the following instruction sequence where registers R1,R2 and R3 are general purpose and MEMORY[X] denotes the content at the memory location X. InstructionMOV R1,(5000)MOV R2,(R3)ADDR2,R1MOV (R3),R2INC R3DEC R1BNZ 1004HALTSemanticsR1←MEMORY[5000]R2←MEMORY[R3]R2←R1+R2MEMORY[R3]←R2R3←R3+1R1←R1−1Branch if not zero to thegiven absolute addressStopInstruction Size (bytes)44242221 Assume that the content of the memory location 5000 is 10, and the content of the register R3 is 3000. The content of each of the memory locations from 3000 to 3020 is 50. The instruction sequence starts from the memory location 1000. All the numbers are in decimal format. Assume that the memory is byte addressable. After the execution of the program, the content of memory location 3010 is
16. The contents of Register (BL) and Register (AL) of 8085 microprocessor are 49H and 3AH respectively. The contents of AL, the status of carry flag (CF) and sign flag (SF) after executing 'SUB AL, BL' assembly language instruction, are a. AL=0FH; CF=1; SF=1 b. AL=F0H; CF=0; SF=0 c. AL=F1H; CF=1; SF=1 d. AL=1FH; CF=1; SF=1
Assume for a given program, 60% of the executed instructionsare of Class A, 10% are of Class B, and 30% are of Class C. Furthermore,assume that an instruction in Class A requires 3 cycles, an instruction inClass B requires 2 cycles, and an instruction in Class C requires 2 tocomplete. i. Compute the overall CPI for this program.ii. Compute the clock rate of the CPU when the time it takes tocomplete 20 instructions is 1.73 ???????????
In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which theprocessor fetches the following instruction word: 10101100100001010000000000011100 Assume that the data memory is all zeros and that the processor’s registers havethe following values at the beginning of the cycle in which the above instructionword is fetched: R0 R1 R2 R3 R4 R5 R6 R8 R12 R31 0 2 4 6 13 10 12 16 24 31 a. What are the outputs of the sign-extend and the jump “Shift-Left-2” (near the topof the following Figure) for this instruction word? (Pic3) b. What are the values of ALU control unit’s inputs (ALUOp and Instruction[5-0])for this instruction? c. What is the new PC address after this instruction is executed? Highlight the paththrough which this value is determined. d. For the ALU and the two add units, what are their data input values? ALU Add (PC+4) Add…
Consider a Computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of 6 addressingmodes, and it has 60 computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory AddressGiven that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction.
A particular (fictional) CPU has the following internal units and timings (WRand RR are write/read registers,ALU does all logic and integer operations and there is a separate floatingpoint unit FPU. Timings for each unit in picoseconds are:IR 230, RR 40, WR 50, ALU 200, MEM 260, FPU 380(assume instruction read and memory access are average time for access tocache)There are 5 basic instruction types: - here are instruction sequence for eachtype, time in picoseconds and percentage of each type in a typical set of testcodes:1. LOAD : IR+RR+ALU+MEM+WR : 780, 20%2. STORE: IR+RR+ALU+MEM : 730, 10%3. LOGIC/INTEGER: IR+RR+ALU+WR : 520, 40%4. FLOATING POINT: IR+RR+FPU+WR : 700, 10%5. BRANCH: IR+RR+ALU : 270, 20%1 cycle is 780ps = .780 nanoseconds for this machine, on the assumption thatall instructions take 1 cycle (assume all memory access is in cache). Clockfrequency is 1/.780 = 1.28 GHz (rounded to 2 decimals) for an ideal CPI=1