Q3 For the resulted design in Q2 how many configurable logic block CLB you would need to implement your design in the FPGA if the CLB structure is as follows

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Q3 For the resulted design in Q2 how many configurable logic block CLB you would need to implement your design in the FPGA if the CLB structure is as follows
Q2: Consider a digital lock that accept 4 binary digits from single input keypad (enter one digit
at a time). It also has two Leds the red is on until the right combination is entered then the
green led is on and the red led is off. Assume the luck is programmed to accept the combination
0110, draw the state diagram and the state table for the digital control circuit of such a digital
lock?
Q3: For the resulted design in Q2, how many configurable logic block (CLB) you would need to
implement your design in the FPGA if the CLB structure is as follows:
Look-Up
Table
MUX
SET
(LUT)
CLR O
Transcribed Image Text:Q2: Consider a digital lock that accept 4 binary digits from single input keypad (enter one digit at a time). It also has two Leds the red is on until the right combination is entered then the green led is on and the red led is off. Assume the luck is programmed to accept the combination 0110, draw the state diagram and the state table for the digital control circuit of such a digital lock? Q3: For the resulted design in Q2, how many configurable logic block (CLB) you would need to implement your design in the FPGA if the CLB structure is as follows: Look-Up Table MUX SET (LUT) CLR O
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