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- Assume that we have a computer with a cache memory of 512 blocks with a total size of 128K bits. Knowing that the computer uses a word addressable mode and the format of the memory address as seen by the Fully associative cache scheme is as shown below, answer the below questions: Fully Associative Cache Format 19 5 1- How many words do we have in each cache block? 2- What is the size of each word? 3- What is the size of the main memory? 4- How many blocks are there in the main memory? 5- Draw the format of the memory address as seen by the Direct Mapped Cache scheme, showing the fields as well as their sizes.A computer is using a fully associative cache and has 216 bytes of main memory (byte addressable) and a cache of 64 blocks, where each block contains 32 bytes. a. How many blocks of main memory are there? b. What will be the sizes of the tag, index, and byte offset fields? c. To which cache set will the memory address 0xF8C9(hexadecimal) map?Q2) Given a physical memory of 8 k and a cache memory of 512 bytes with block size 64 bytes. The system uses set associative mapping with set size 2 lines per set A- How many sets we will have in the cache memory b-B- How the address will be split to indicate tag, set no, and offset c-Calculate the cache address (set, line no, and offset) that physical address 140 will be mapped.
- Assume that we have a computer with a cache memory of 512blocks with a total size of 128K bits. Knowing that the computer uses a word addressable mode and the format of the memory address as seen by the Fully associative cache scheme is as shown below, answer the below questions: Fully Associative Cache Format 1- How many words do we have in each cache block? 2- What is the size of each word? 3- What is the size of the main memory? 4- How many blocks are there in the main memory? 5- Draw the format of the memory address as seen by the Direct Mapped Cache scheme, showing the fields as well as their sizes.A 32-bit computer has a memory of 256 KB and a cache line size of 64 bytes. The memory cache access time is 5ns. This cache is 4-way associative and use LRU as a replacement algorithm. a) What is the number of lines and sets of this memory cache? b) What is the block size transferred between the cache memory and the main memory? c) If the time to transfer a line to cache memory is 200 ns, what is the hit ratio needed to obtain an average access time of 20 ns?Show work and type answer please. Suppose a computer using fully associate cache has 2G Bytes of main memory and a cache of 256 Blocks, where each cache Block has 8 Words, and the Word Size is 2 Bytes. a. How many blocks of main memory? b. What is the format of a memory address as seen by the cache? c. To which cache block will the memory reference 00001C4A in Hex?
- A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.Q2) Given a physical memory of 8 k and a cache memory of 512 bytes with block size 64 bytes. The system uses associative mapping with set size 2 lines per setA- How the memory address will be split to indicate tag, and offset B- What is the size of tag directory.You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set-associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a letter. Two blocks equal one frame. Given the system state as depicted above, How many bits are in a physical address? Explain.
- You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set-associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a letter. Two blocks equal one frame. Given the system state as depicted above, Given virtual address 0x06 converts to physical address 0x36. Show the format for a physical address (specify the field names and sizes) that is used to determine the cache location for this address. Explain how to use this format to determine where physical address 0x36 would be located in cache. (Hint: Convert 0x36 to binary and divide it into the appropriate fields.)Assume we have a computer with 512 blocks of cache memory with a total capacity of 128K bits. Answer the following questions knowing that the computer operates in a word addressable mode and that the format of the memory address as perceived by the Fully associative cache scheme is as shown below: Cache Format with Full Associativity 19 5 1- How many words are in each cache block? 2- How big are the letters in each word? 3- How large is the primary memory? 4- What is the total number of blocks in main memory? 5- Draw the memory address format as observed by the Direct Mapped Cache technique, including the fields and their sizes.A computer system has 32 address lines and 16K bytes cache. Each cache block size is 32 bytes. For the following cases, (a) a direct mapped cache (b) a fully associative cache (c) a 4-way set associative cache (1) How many comparators are required in each cases? (2) When the CPU references an address 0xABCDEF12, what is the tag value for each cases?