Page Frame 4 1 TLB TAG DATA TAG DATA Set 0 00 Set 1 00 01 10 н Cache Frame Valid 3 Page table Block Frame 2 3 2 T.... Н .... 3. 1. 012 34 567 Main memory Page Block 4 8 10 5 11 12 6. 13 14 15 Virtual memory for process P ABCDEEGHISYLMNOP 1. 2. 4.

You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set-associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a letter. Two blocks equal one frame.

Given the system state as depicted above, Given virtual address 0x06 converts to physical address 0x36. Show the format for a physical address (specify the field names and sizes) that is used to determine the cache location for this address. Explain how to use this format to determine where physical address 0x36 would be located in cache. (Hint: Convert 0x36 to binary and divide it into the appropriate fields.)