Question 2 (8) i) Processor having Clock cycle of 0.25ns will have clock rate of a) 2GHZ b) 3GHZ c) 4GHZ d) 8GHZ ii) If computer A executes a program in 10 seconds and computer B runs the same program in 15 seconds, what is the relative performance of computer A compared to computer B? a) 1.4 b) 1.5 c) 0.67 d) 1 iii) architecture implies, arithmetic and logic operations can only take place between CPU registers. iv) Using the following instruction format, a total of registers can be addressed. 8 7 10 OP code Source Dest Other info

Question 2 (8) i) Processor having Clock cycle of 0.25ns will have clock rate of a) 2GHZ b) 3GHZ c) 4GHZ d) 8GHZ ii) If computer A executes a program in 10 seconds and computer B runs the same program in 15 seconds, what is the relative performance of computer A compared to computer B? a) 1.4 b) 1.5 c) 0.67 d) 1 iii) architecture implies, arithmetic and logic operations can only take place between CPU registers. iv) Using the following instruction format, a total of registers can be addressed. 8 7 10 OP code Source Dest Other info

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Section 1.0 cites as a pitfall the utilization of a subset of the performace equation as a performance metric. To illustrate this, consider the following two processors. P1 has a clock rate of 4GHz, average CPI of 0.9, and requires the execution of 5.0E9 instructions. P2 has a clock rate of 3GHz, an average CPI of 0.75, and requires the execution of 1.0E9 instructions. (1) A common fallacy is to use MIPS to compare the performace of two different processors, and consider that the processor with the largest MIPS has the largest performance. Check if this is true for P1 and P2. (2) Another common performace figure is MFLOPS, defined as MFLOPS = No. FP operations / (execution time x 1E6) but this figure has the same problems as MIPS. Assume that 40% of the instructions executed on both P1 and P2 are floating-point instructions. Find the MFLOPS figures for the processors.
15.a) Consider an instruction pipeline with four stages with the stage delays 5 nsec, 6 nsec, 11 nsec, and 8 nsec respectively. The delay of an inter-stage register stage of the pipeline is 1 nsec. What is the approximate speedup of the pipeline in the steady-state underideal conditions as compared to the corresponding non-pipelined implementation? b) Discuss structural hazards and control hazards with examples pls answer both subparrts,,its urgent thanks
Assume for arithmetic, load/store, and branch instructions, a processor has CPIs for 1, 12, and 5respectively. Also assume that on a single processor a program requires the execution of 2.56*10^9arithmetic instructions, 1.28*10^9 load/store instructions, and 256 million branch instructions. Assumethat each processor has a 2GHz clock frequency. Assume that, as the program is parallelized to run overmultiple cores, the number of arithmetic and load/store instruction per processor is divided by 0.7xp(where p is the number of processors) but the number of branch instructions per processor remains thesame. a- Find the total execution time for the program on 1,2,4, and 8 processors, and show the relativespeedup of the 2,4, and 8 processor result relative to single processor result. b- If the CPI of the arithmetic instruction was doubled, what would be the impact be on theexecution time of the program on 1,2,4, and 8 processors? c- To what should the CPI of load/store instructions be…
1. We wish to compare the performance of two different machines: M1 and M2. The following measurements have been made on these machines: Program Time on M1 Time on M2 1 10 seconds 5 seconds 2 3 seconds 4 seconds Which machine is faster for each program, and by how much? 2. For M1 and M2 of problem 1, the following additional measurements are made:. Find the instruction execution rate (instructions per second) for each machine when running program 1. Program Instructions executed on M1 Instructions executed on M2 1 200 x 106 160 x 106 3. For M1 and M2 of problem 1, if the clock rates are 200 MHz and 300 MHz, respectively, find the CPI for program 1 on both machines using the data provided in problems 1 and 2. 4. You are going to enhance a machine, and there are two possible improvements: either make multiply instructions run four times faster than before or make memory access instructions run two times faster than before. You…
1. Develop a mathematical model for measuring performance based on overall memory access time with a neat diagram for the following memory design and derive the formula to calculate the Overall Memory Access Time. Main Memory : 1 Internal Cache : 1 External Cache: 1 Register S and Register B have fastest access time: Data Search order [ Registers – Internal Cache – External Cache – Memory] [Hint: Register access time is considered negligible]
- Consider that each instruction require 6 steps (phases) to execute and each (step) phase takes 5 seconds to complete. Also, within each instruction it requires 3 seconds time gap between end of completion one step (phase) and beginning of next step (phase). b. Design and reflec on a suitable pipeline technique using which time taken for executing all 3 programs can be further improved. Calculate the improved time using this method by considering that instruction require same number of steps to complete and time taken for each step is same and time gap between each steps is also same?
Suppose you are developing a processor with an execution time of 960 ns, CPI of 1.61, and clock rate of 3 GHz. If the execution time is reduced by an additional 20% without affecting to the CPI and with a clock rate of 4 GHz, determine the number of instructions.
Assume for arithmetic, load/store, and branch instructions, a processor has CPIs of 1, 12, and 5, respectively. Also assume that on a single processor a program requires the execution of 2.56E9 arithmetic instructions, 1.28E9 load/store instructions, and 256 million branch instructions. Assume that each processor has a 2 GHz clock frequency. Assume that, as the program is parallelized to run over multiple cores, the number of arithmetic and load/store instructions per processor is divided by 0.7 x p (where p is the number of processors) but the number of branch instructions per processor remains the same. Find the total execution time for this program on 1, 2, 4, and 8 processors, and show the relative speedup of the 2, 4, and 8 processor result relative to the single processor result. If the CPI of the arithmetic instructions was doubled, what would the impact be on the execution time of the program on 1, 2, 4, or 8 processors? To what should the CPI of load/store instructions be…
Assume in a computer A, the execution time equals 960 ns, CPI of 1.61, and clock rate of3GHz. If the execution time is reduced by additional 10% without affecting the CPI and with aclock rate of 4 GHz, determine the number of instructions.
SUBJECT: COMPUTER ORGANASATION 1. a. How many address bits are required to access 256K words of memory? b. How many bytes of memory can be addressed by 24 address bits?
Example 2: Define machine cycle, describe the contents of the address, data and control bus lines when the instruction MOV (2400H], BX is executed. Assume that register DS = 2000H and register BX = 1234H.
Please solve and show all work and steps. Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 3 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and a CPI of 2.2. Which processor has the highest performance expressed in instructions per second? If the processors each execute a program in 15 seconds, find the number of cycles and the number of instructions?