QUESTION 22 We have a system with a CPU and several peripheral devices connected via address and data buses. If the address bus width is 16, conceivably how may peripheral devices can the CPU connect to? O 1k O 64k O 32k O 16k QUESTION 23 Fast, memory built inside the CPU to enhance performance: O L1, L2 and L3 cache O Dynamic RAM

Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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QUESTION 22
We have a system with a CPU and several peripheral devices connected via address and data buses.
If the address bus width is 16, conceivably how may peripheral devices can the CPU connect to?
O 1k
O 64k
O 32k
O 16k
QUESTION 23
Fast, memory built inside the CPU to enhance performance:
O L1, L2 and L3 cache
O Dynamic RAM
ROM
dual processor
QUESTION 24
1Meg is specified in as 2 raised to what power [just provide the numerical exponent, don't write 2 or any extra
characters) ?
QUESTION 25
We are designing a custom computer, Our CPU is to be connected to RAM with 4GB Capacity (this means the RAM
stores data 1Byte in the x-direction, and 4G in the y-direction).
What is the required address bus width between the CPU and RAM to support 4G discrete addresses? Just offer the
exact numerical answer, no extra words. For example if the answer were 5, don't write "5 bits."
Transcribed Image Text:QUESTION 22 We have a system with a CPU and several peripheral devices connected via address and data buses. If the address bus width is 16, conceivably how may peripheral devices can the CPU connect to? O 1k O 64k O 32k O 16k QUESTION 23 Fast, memory built inside the CPU to enhance performance: O L1, L2 and L3 cache O Dynamic RAM ROM dual processor QUESTION 24 1Meg is specified in as 2 raised to what power [just provide the numerical exponent, don't write 2 or any extra characters) ? QUESTION 25 We are designing a custom computer, Our CPU is to be connected to RAM with 4GB Capacity (this means the RAM stores data 1Byte in the x-direction, and 4G in the y-direction). What is the required address bus width between the CPU and RAM to support 4G discrete addresses? Just offer the exact numerical answer, no extra words. For example if the answer were 5, don't write "5 bits."
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