Question 3: PLDS & Gate Delay 1. Consider the below PAL. Find the logic expression of the outputs W, X and Y. Do not simplify. **
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- i): Implement the Boolean function ? = ??̅? using 2-input NAND gates in optimized manner. ii): An Exclusive-OR gate has the following Boolean expression: Draw the schematic diagram for said Boolean expression entirely from NAND gates.Use Digital Logic Simulator Fill-in the blank boxes with the correct LOGIC GATE/ Full/Half AdderQ (A, B, C) = A' .B'. C +A' .B. C + A.B.C' + A.B.C Obtain the simplified function with the Karnaugh Map method in terms of minterms and maxters separately. Set the output functions separately with logic gates with ANDNOT for minterms and ORNOT for maxterms.
- What is a transmission gate? Draw its circuit circuit diagram. How does it operate? What is the need for a transmission gate? What is it disadvantage?We want to design a circuit to detect prime numbers.The input of the circuit is a 4-bit binary number and the output is a single bit and should show one when the number is prime and zero otherwise.B. Implement the circuit using a 4× 1 multiplexer and combinational logic gates.C. Implement the circuit using only one decoder and one OR gate. What is the size of the decoder you use?(a) Differentiate comparatively the analogue and digital representations. (b) If 33210= Xs then find the value of X. (c)1001011.0112 to equivalent decimal (d) What do you know about the logic gates? Explain the AND gate in details. 410 A
- Draw the logic diagram for the following functions, then map it using NAND only technology and NOR only technology: Y = A’B’ + B (A + C)+ C’D+ DF(a,b,c,d)=ab'+c'd'+a'cd' Perform the function in accordance with the following styles using the Karnaugh diagram. Draw each simplification using the corresponding logic gates. a) only or not (NOR) b) and not just (NAND) c) OR-NAND d) AND-NORRealize the following function ; " on the image " using a(a) 4-to-1 multiplexer, and draw the logic diagram.(b) 8-to-1 multiplexer, and draw the logic diagram.You may use external gates if needed.
- Draw the logic diagram for the following functions, then map it using NAND only technology and NOR only technology: F = y’z + y(x + w) Y = A’B’ + B (A + C)+ C’D+ DCreate the logic diagram of the two bits full adderPerform the functions given below with the decoder given below and a suitable logic gate. F1(A,B, C) = ∑m( 3, 5, 6) F2(A,B, C) =∑m ( 1, 4)