0 1 1100 1Question:4. FIGURE 1 shena how a 3 to S line decoder (TTL 74138) can be uaed in conjunction with NAND gare (TTL 14133) to connect a set of switches to the data bua of a microprocessor system via buffen (TTL 74367)Answer the following questions relating to the diagram2) What address, in HEX, is required on the zdáress bus in order toread the switches?b) RD and MENRÇare control lines from the CPU. What must theirlogic state be in order to read the swvitches?Data bus74 36774 13374 138A15D7DOENENAddressbusRDMEMROA3A2A1eTRUTH TABLEENCBAO 120 0 11011 1 1 110 101 101 1 1 1174 367(part of)10 11 1 1110 111101 111110111111i11110FIGURE 1Data enablesundyno edInput switches

1.The address is A3 in HEX, is required on the address bus in order to read the switches

Question: 4 FIGURE 1 showa how a 3 to S line decoder (TIL 74135) can be uaed in conjunction with NAND gre (TTL 74133) to comnect a set of switches to the data bua of 2amicroprocessor system víe buffers (TTL 74367). Answer the following questiona relating to the diagam ) What address, in HEX a required on the zdáress bus in arder toread the switches? b) RD and MEMRQare control lines from the CPU. What muat their ogic state be in order to read the switches Data bus 74 367 74 133 74 138 A15 D7 DO EN EN Address bus RD A3 A2 A1e AO MEMRO A4 EN TRUTH TABLE BAIO 0 0 110 0 1011 0 1 111 10 0i ii 10 111i1 110111i 11 111111 74 367 (part of) Data enable Data outputs Input switches

Question: 4 FIGURE 1 showa how a 3 to S line decoder (TIL 74135) can be uaed in conjunction with NAND gre (TTL 74133) to comnect a set of switches to the data bua of 2amicroprocessor system víe buffers (TTL 74367). Answer the following questiona relating to the diagam ) What address, in HEX a required on the zdáress bus in arder toread the switches? b) RD and MEMRQare control lines from the CPU. What muat their ogic state be in order to read the switches Data bus 74 367 74 133 74 138 A15 D7 DO EN EN Address bus RD A3 A2 A1e AO MEMRO A4 EN TRUTH TABLE BAIO 0 0 110 0 1011 0 1 111 10 0i ii 10 111i1 110111i 11 111111 74 367 (part of) Data enable Data outputs Input switches

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 30VE

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