Read the following description concerning a logic circuit, and then answer Subquestions 1 and 2

Electric Motor Control
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Chapter22: Sequence Control
Section: Chapter Questions
Problem 6SQ: Draw a symbol for a solid-state logic element AND.
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Q1. Read the following description concerning a logic circuit, and then answer Subquestions 1 and 2.

 

Figure 1 shows a logic circuit that is used as a control system for an electronic device. The logic circuit has three inputs (X, Y and Z) and one output (F).  As shown in Figure 1, the logic circuit has a feed back line, by which the last output F is fed back and is used as the current input to the NAND gate.  Therefore, the current output F is determined by three current inputs X, Y and Z and the last output F.  In this control system, among three inputs X, Y and Z, at most only one input can change its value on each clock cycle.

 

                                                             (Feed back line)

Figure 1  The logic circuit

 

Meanings of the logic gate symbols used in Figure 1 are as follows:

             AND gate       NAND gate     OR gate           NOR gate

                                                        

 

Figure 2 shows sample input/output status of the logic circuit.  For example, the output F on the clock cycle c (value 0) is obtained from the inputs X, Y and Z on the clock cycle c (values 1, 0 and 1 respectively) and the output F at the clock cycle c-1 (value 0).

 

 

             Clock cycle   |       c - 1       |          c          |       c + 1       |     …

 

Figure 2  Sample input/output status of the logic circuit

 

Subquestion 1

From the answer group below, select the correct answer to be inserted into each blank

_______ in the following three figures.  If necessary, select the same answer twice or more.

 

 

 

 

Answer group

 

Subquestion 2

From the answer group below, select the correct answer to be inserted into the blank _______ in the following description.

 

When the value 1 is obtained on the clock cycle c at the intermediate point T in Figure 1, it is always true that ____D____.

 

Answer group

  1. the output F on the clock cycle c-1 was 0
  2. the output F on the clock cycle c-1 was 1
  3. both of inputs X and Y on the clock cycle c are 0
  4. both of inputs X and Y on the clock cycle c are 1

 

Q1. Read the following description conceming a logic circuit, and then answer Subquestions
I and 2.
Figure I shows a logic circuit that is used as a control system for an electronic device.
The logic circuit has three inputs (X, Y and Z) and one output (F). As shown in Figure 1,
the logic circuit has a feed back line, by which the last output F is fed back and is used as
the current input to the NAND gate. Therefore, the current output F is determined by three
current inputs X, Y and Z and the last output F. In this control system, among three inputs
X, Y and Z, at most only one input can change its value on each clock cycle.
(Feed back line)
Figure 1 The logic circuit
Meanings of the logic gate symbols used in Figure I are as follows:
AND gate
NAND gate OR gate
NOR gate
Figure 2 shows sample input/output status of the logic circuit. For example, the output F
on the clock cycle ce (value 0) is obtained from the inputs X, Y and Z on the clock cycle e
(values 1,0 and I respectively) and the output F at the clock cycle c-1 (value 0).
-4 -
Clock cycle |
c- 1
c+1
...
1
Y
F
Question
Answer :
Figure 2 Sample input/output status of the logic circuit
Subquestion 1
From the answer group below, select the correct answer to be inserted into each blank
in the following three figures. If necessary, select the same answer twice or
more.
Transcribed Image Text:Q1. Read the following description conceming a logic circuit, and then answer Subquestions I and 2. Figure I shows a logic circuit that is used as a control system for an electronic device. The logic circuit has three inputs (X, Y and Z) and one output (F). As shown in Figure 1, the logic circuit has a feed back line, by which the last output F is fed back and is used as the current input to the NAND gate. Therefore, the current output F is determined by three current inputs X, Y and Z and the last output F. In this control system, among three inputs X, Y and Z, at most only one input can change its value on each clock cycle. (Feed back line) Figure 1 The logic circuit Meanings of the logic gate symbols used in Figure I are as follows: AND gate NAND gate OR gate NOR gate Figure 2 shows sample input/output status of the logic circuit. For example, the output F on the clock cycle ce (value 0) is obtained from the inputs X, Y and Z on the clock cycle e (values 1,0 and I respectively) and the output F at the clock cycle c-1 (value 0). -4 - Clock cycle | c- 1 c+1 ... 1 Y F Question Answer : Figure 2 Sample input/output status of the logic circuit Subquestion 1 From the answer group below, select the correct answer to be inserted into each blank in the following three figures. If necessary, select the same answer twice or more.
Subquestion 1
From the answer group below, select the correct answer to be inserted into each blank
in the following three figures. If necessary, select the same answer twice or
more.
Y
F
A
Y
1.
F
B
Y
F
Answer group
a)
b)
c)
1
1
1
f)
1
h)
1
Subquestion 2
From the answer group below, select the correct answer to be inserted into the blank
]in the following deseription.
When the value I is obtained on the clock cycle e at the intermediate point T in Figure 1, it
is always true that [
Answer group
a) the output F on the clock cycle e-1 was 0
b) the output F on the clock cycle c-1 was 1
c) both of inputs X and Y on the elock cycle e are 0
d) both of inputs X and Y on the clock cycle c are 1
Transcribed Image Text:Subquestion 1 From the answer group below, select the correct answer to be inserted into each blank in the following three figures. If necessary, select the same answer twice or more. Y F A Y 1. F B Y F Answer group a) b) c) 1 1 1 f) 1 h) 1 Subquestion 2 From the answer group below, select the correct answer to be inserted into the blank ]in the following deseription. When the value I is obtained on the clock cycle e at the intermediate point T in Figure 1, it is always true that [ Answer group a) the output F on the clock cycle e-1 was 0 b) the output F on the clock cycle c-1 was 1 c) both of inputs X and Y on the elock cycle e are 0 d) both of inputs X and Y on the clock cycle c are 1
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