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- Follow this steps. Have to Consider two different implementations, M1 and M2, of the same instruction set. There arethree classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies(for a typical program) are as follows:Instruction Class M1-Cycles/InstructionClass M2 -Cycles/InstructionClasss FrequencyA 1 2 60%B 3 2 30%C 4 3 10%(a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2.(c) Which machine has a smaller MIPS rating? Which individual instruction class CPI do you needto change, and by how much, to have this machine have the same or better performance as themachine with the higher MIPS rating (you can only change the CPI for one of the instructionclasses on the slower machine)?.Consider two different implementations, M1 and M2, of the same instruction set. There arethree classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies(for a typical program) are as follows:Instruction Class M1-Cycles/InstructionClass M2 -Cycles/InstructionClasss FrequencyA 1 2 60%B 3 2 30%C 4 3 10%(a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2.(c) Which machine has a smaller MIPS rating? Which individual instruction class CPI do you needto change, and by how much, to have this machine have the same or better performance as themachine with the higher MIPS rating (you can only change the CPI for one of the instructionclasses on the slower machine)?Consider a 32-bit computer with the MIPS assembly set, that executes the following code fragment loaded in memory in the address 0x0000000. li $t0, 1000 li $t1, 0 li $t2, 0 loop: addi $t1, $t1, 1 addi $t2, $t2, 4 beq $t1, $t0, loop This computer has a 4-way associative cache memory of 32 KB and lines of 16 bytes. Calculate the number of cache miss of the previous code, and the hit ratio, assuming that no other program is executing and that the cache memory is initially empty.
- Consider a machine with three instruction classes and CPI measurements as follows: Instruction class CPI of the instruction class A 2 B 5 C 7 Suppose that we measured the code for a given program in two different compilers and obtained the following data: Code sequence Instruction counts (in millions) A B C 1 15 5 3 2 25 2 2 Assume that the machine’s clock rate is 500 MHz. Which code sequence will execute faster according to MIPS? How much according to execution time of each code sequence?Take the multiprocessor with 30 processors, each processor is capable od max2Gflops. What is the maximum capability of the multiprocessor for the execution of anapplication that has 5% sequential code?Computer Science 1 .Consider the task of doubling all the elements of a 8192 element vector, which might be done on a SISD machine by the following code. Suppose each iteration of the loop requires 20 clock cycles - so the whole process needs 163,840 clocks. for (int i = 0; i < 8192; i ++) x[i] *= 2.0; Now suppose, instead, that the process is done on a pipelined processor having a single pipeline that supports memory to memory vector operations. Assume that each computation (fetch x[i], double it, store result) still takes 20 clock cycles, but that the pipeline, once full, can produce one result each cycle. How many clock cycles total will be needed for this case?
- Consider a multilevel computer in which levels are vertically stacked, with the lowest level being level 1. Each level has instructions that are m times as powerful as those of the level below it; that is, one level r instruction can do the work of m instructions at level r-1. However, n instructions at level r-1 are required to interpret each instruction at level r. Given this, answer the following questions: If a level 1 program requires k seconds to run, how long would the equivalent program take to run at levels 2, 3 and 4. Express your answer in terms of n, m, and r. What is the performance implication for the program if n > m? Conversely, what is the implication if m > n? Which case do you think more likely? Why?2. Suppose we have two implementations of the same instruction set architecture.Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some programand computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the sameprogram. Which computer is faster for this program and by how much?A 32-bit computer has 32 registers, and a memory addressed by bytes with two cycles for reading and writing operations. Consider the instruction ADD, R1, addr. This instruction adds the value stored in R1 to the value stored in the memory address addr, and stores the result in the register R1. a) Show a possible format for this instruction, having into account that the computer has 100 machine instructions and the addresses are represented using 32 bits. b) Indicate the elemental operations and control signals needed to execute the previous instruction.
- In this exercise, we examine in detail how much an instruction is executed in a single-cycle Datapath. The problem refers to a clock cycle in which the processor fetches the following instruction word: 1010 1100 0110 0010 0000 0000 0001 0100. Assume that data memory is all zeros and that the processor's registers have the following values at the beginning of the cycle in which of the instruction word is fetched: (See image attached) What is the new PC address after this instruction is executed? Highlight the path through which this value is determined?Two algorithms A and B report time complexities expressed by the functions n2and 2n , respectively. They are to be executed on a machine M that consumes 10–6 s to execute an instruction. What is the time taken by the algorithms to complete their execution on machine A for an input size of 50? If another machine N that is 10 times faster than machine M is provided for the execution, what is the largest input size that can be handled by the two algorithms on machine N? What are yourobservations?hi can u anwser this qustion plesc ? Consider a Computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of “K” addressing modes, and it has “M” computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory AddressGiven that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction.Note: Choose your own values for K (number of addressing modes) and M (number of Registers) k=8 m=50