Repeater Example Example 6.10 Compute the delay per mm of a repeated wire in a 65 nm process. Assume the wire is RW on a middle routing layer and has 2x width, spacing, and height, so its resistance is 200 2/mm and capacitance is 0.2 pF/mm. The FO4 inverter delay is 15 ps. Also find the repeater spacing and driver size to achieve this delay and the energy per bit. SOLUTION: Using EQ (6.29), the delay is 'N =(2+ √2(1+ Pm))√RCRC = 1.67 √FO4 R_C_ p = 1.67√(15 ps) (200 2/mm)(0.2 pF/mm) = 41 ps/mm (6.32) This delay is achieved using a spacing of 0.45 mm between repeaters and an nMOS driver width of 18 um (180x unit size). The energy per bit is 0.4 pJ/mm. ③ Energy / length 1.87CwVDD2 14: Wires CMOS VLSI Design 4th Ed. 33 33

Repeater Example Example 6.10 Compute the delay per mm of a repeated wire in a 65 nm process. Assume the wire is RW on a middle routing layer and has 2x width, spacing, and height, so its resistance is 200 2/mm and capacitance is 0.2 pF/mm. The FO4 inverter delay is 15 ps. Also find the repeater spacing and driver size to achieve this delay and the energy per bit. SOLUTION: Using EQ (6.29), the delay is 'N =(2+ √2(1+ Pm))√RCRC = 1.67 √FO4 R_C_ p = 1.67√(15 ps) (200 2/mm)(0.2 pF/mm) = 41 ps/mm (6.32) This delay is achieved using a spacing of 0.45 mm between repeaters and an nMOS driver width of 18 um (180x unit size). The energy per bit is 0.4 pJ/mm. ③ Energy / length 1.87CwVDD2 14: Wires CMOS VLSI Design 4th Ed. 33 33

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

See similar textbooks

Similar questions

Design an asymmetrical inverter to meet the delay of 250 ps for a load capacitance of 120 fF. Use VDD =1.5V, VTN =0.50 V, and VTP =−0.50 V. with (W/L)P = (W/L)N .
(a) The n-well in a CMOS process covers an area of 1 cm× 0.5 cm, and the junction saturation current density is 500 pA/cm2. What is the total leakage current of the reverse-biased well? (b) Suppose the drain and source regions of the NMOS and PMOS transistors are 2µm × 5µm, and the saturationcurrent density of the junctions is 100 pA/cm2. If the chip has 20 million inverters, what is the total leakage current due to the reverse-biased junctions when vO =2.5 V? Assume VDD =2.5 V and VSS =0 V. (c) When vO =0 V?
Find the ratio of hole mobility to electron mobility of a CMOS inverter given that the beta ratio of pull-up network to pulldown network is 1.5 (Assume that W/L ratio of pMOS is 3 times greater than that of nMOS and all other parameters are same for both) Assuming the supply voltage to be 3V draw a suitable DC transfer characteristic curve of the CMOS inverter.
Design an asymmetrical inverter to meet the delay specification a symmetrical CMOS reference inverter to provide a propagation delay of 400 ps fora load capacitance of 200 fF. Use VDD =2.5 V, VTN =0.60 V, and VTP =−0.60 V.with (W/L)P = (W/L)N .
Suppose the ECL inverter as shownmust operate at a power of 20 W. If the currentsources are scaled by the same factor, and the capacitancesand voltage levels remain the same, whatis the new propagation delay of the inverter?
Perform a 1000 case Monte Carlo analysis forthe noise margins of the inverter if thethreshold voltage has a tolerance of 10 percent,the power supply has a 5 percent tolerance andKn and R both have 30 percent tolerances. Whatare the nominal, minimum and maximum values ofNML and NMH ? (b) Compare the results
Q3 Design parallel inverter to generate s mmzmmummm resistive load 120W,240Y, if the batiery voltage is 12V,
Justify the usage of the RCD (residual current device ) at the AC side of the inverter? You have to explain its operation prinviple
(a) What is the power-delay product for a symmetrical CMOS inverterwith (W/L)N =2/1, (W/L)P =5/1, C =0.25 pF,VDD =3.3 V, VTN =0.75 V, and VTP =−0.75 V? (b) Estimate the maximum switchingfrequency for this inverter. (c) Howmuch powerdoes the inverter dissipate if it is switching at thefrequency found in (b)?
What are the noise margins for a symmetrical CMOS inverter operating with VDD = 3.3 V and VTN = −VTP = 0.75 V? (b) Repeat for a CMOS inverter having (W/L)N = (W/L)P operating with VDD = 3.3 V and VTN = −VTP = 0.75 V.
The graph gives the results of aSPICE simulation of an inverter. (a) What are therise and fall times for vI and vO ? (b) What are thevalues of τPHL and τPLH ? (c) What is the averagepropagation delay for this gate? (d) What will be theaverage propagation delay if the load capacitanceis doubled?
'Home work (4) If the bridge inverter is loaded by an R-L laod with R=20 ©, L=30 mH. The inverter frequency, f,=50 Hz and the de input voltage, Vs=200 V. (@) Express the instantaneous load current in fourrier series. (b) Caleulate : i The rms load current at the fundamental frequency fi il The THD of the load current. iii. The power obserbed by the load (Po) and the fundamental power (Pol). Draw the waveform of the fundamental load current and show the intervals of transistors and diodes conduction.