Show your work 1- What will be the waiting time for p3 if we applied FCFS sceduling algorithm.
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- Answer the following:I. Name any two interrupt/exceptions that can occur during IF and ID stagesII. Contrast superscalar and superpipelined modes of ILPIII. What is the role of write back buffers in write-through and write-back cachesIV. What is the impact of prefetcher on the different kinds of cache missesV. Illustrate why and what kind of hazards are addressed/not-addressed by registerrenamingComputer Science Create a PowerShell script that handles the following information. The script must utilize an arrays and loop. $server1 = "Mercury" $server2 = "Venus" $server3 = "Mars" $server4 = "Pluto" Write-Host "$server1 has been backed up" Write-Host "$server1 has been updated" Write-Host "$server1 has been received vendor files" Write-Host "$server2 has been backed up" Write-Host "$server2 has been updated" Write-Host "$server2 has been received vendor files" Write-Host "$server3 has been backed up" Write-Host "$server3 has been updated" Write-Host "$server3 has been received vendor files" Write-Host "$server4 has been backed up" Write-Host "$server4 has been updated" Write-Host "$server4 has been received vendor files" Answer SkipThe NX (“no execute”) bit can also be supported by modern CPUs. To force a CPU to avoid running the code on a file, set the NX bit to 1 on that page. Currently, the OS and paging hardware implement this maximum quantity. Keep in mind that non-X86-compliant software/hardware can be executed on an OS and hardware How about a parser who wants to enforce NX above the operating system level? The programmer inserts a nX-bit association with each memory page at the bottom (in other words, at each memory location of nX bits.) The programmer imposes a size limit of 4095 bytes for application-level data structures. each stack frame is allocated in its own page, and no stack frame is larger than a page. At a given point in time, a stack frame might look like this: |-----------------------| | | +-----------------------+ entry %esp-->| return address | +-----------------------+ new %ebp---->| saved %ebp | +-----------------------+ | buf[4] | | buf[3] | | buf[1] | | buf[0] |…
- Suppose, you need to service 36 interrupts. At least how many slave-8259chips do you need to fulfil this requirement? Again, let, you need one more interrupt to servicealongside the above 36. Would you need more slave-8259? Explain shortly.Question 7 A serial transmitter with event: Tr_buf is a byte-wide buffer. Serially output its content on a serial line. When Tr_buf is empty, set event TR. On TR event, load Tr_buf from bottom of FIFO. write a verlog code using bhevarioial level Full explainthe this question very fast solution sent me step by step Don't ignore any part all part work u Text typing work only not allow paper workWhich of following is not true for virtual memory? a)In page table of virtual memory, if valid-invalid bit is invalid, then whether the page is in secondary storage or page is not in logical address space of that process b)A page fault occurs when a virtual adress that is referenced is not already loaded into physical address c)A program must be loaded to physical memory (RAM) completely for it to be executed d)Virtual memory makes it possible to execute programs that are larger than physical memory(RAM).
- Consider the following scenario:a main program starts execution at time t = 03 second later device B sends interrupt signal5 second later device A sends interrupt signal2 second later device E sends interrupt signal3 second later device C sends interrupt signal5 second later device D sends interrupt signal5 second later device F sends interrupt signalhighlight on the following figure the paths of execution that realize the mentioned interrupt scenario.With each highlighted path indicate time value (t = ?)Finally draw one more path from the last ISR executed back to the main program and displayreturn time.Assume there is a PCI buffer that is used for data transfers between primary memory and a webcam. The memory transfers 15 frames where each frame is 1M byte in size and the buffer size is 1K byte. 1-How many data transfers will be required? 2-A transfer operation requires 2 interrupts. Start and stop. How many interrupts will occur for the data transfer? 3-What are the two commands that will be issued by the supervisor for each interrupt?Suppose the Vole communicates with a printer using the technique of memory-mapped I/O. Suppose also thataddress 0xFF is used to send characters to the printer, and address 0xFE is used to receive information about theprinter’s status. In particular, suppose the least significant bit at the address 0xFE indicates whether the printeris ready to receive another character (with a 0 indicating “not ready” and a 1 indicating “ready”). Starting ataddress 0x00, write a machine language routine that waits until the printer is ready for another character and thensends the character represented by the bit pattern in register 0x5 to the printer.
- For this assignment, you will create a parallel fixed-length code decompressor using the tools we learned in class to create multiple processes and threads. Computers represent a character as a sequence of 8 bits, which means you can represent up to 256 symbols per character. However, depending on the source, it is common to have messages/files using an alphabet with a size of fewer than 256 symbols. The simplest way to achieve compression is to use a fixed-length code generator. The idea behind this type of code generator is to assign a fixed-length bit sequence to each alphabet symbol. Given an alphabet (where each symbol is represented by a character and a decimal value with the code of the symbol), you need to implement a fixed-length code decompressor based on the following steps: ◦Read the contents of the input file using input redirection (STDIN). The format of the input file is as follow: - An integer value representing the number of symbols in the alphabet - n lines (where…⦁ You are required to make changes in the programs and introduce the use of compaction where required. MVT MEMORY MANAGEMENT TECHNIQUE#include<stdio.h>#include<conio.h>main(){int ms,mp[10],i, temp,n=0; char ch = 'y';clrscr();printf("\nEnter the total memory available (in Bytes)-- "); scanf("%d",&ms);temp=ms;for(i=0;ch=='y';i++,n++){printf("\nEnter memory required for process %d (in Bytes) -- ",i+1); scanf("%d",&mp[i]);if(mp[i]<=temp){printf("\nMemory is allocated for Process %d ",i+1); temp = temp - mp[i];}else{printf("\nMemory is Full"); break;}printf("\nDo you want to continue(y/n) -- "); scanf(" %c", &ch);}printf("\n\nTotal Memory Available -- %d", ms);printf("\n\n\tPROCESS\t\t MEMORY ALLOCATED "); for(i=0;i<n;i++)printf("\n \t%d\t\t%d",i+1,mp[i]); printf("\n\nTotal Memory Allocated is %d",ms-temp);printf("\nTotal External Fragmentation is %d",temp); getch();Computer Science 6. (Interrupt - 20) a. What we mean by ISR? explain and give example b. What is the purpose of the NVIC? explain c. How priority works on MSP432? And how many levels there are? Given that two processes with different priorities which will be executed first, and on what basis? d. Let us say you want to configure an interrupt with exception number 40. Which one of the followings is correct way to set the enable register? NVIC->ISER[1] or NVIC->ISER[0] and why?