Suppose that each of the 4 processors in a shared memory multi-processor system is rated at 400 MIPS. A program contains a purely sequential part that accounts for 22% of the program’s execution time on a single processor. The remaining code can be partitioned into three independent parts (A, B, and C). Running on a single processor, part A accounts for 30% of the program’s execution time, part B accounts for 18%, and part C accounts for 30%. What is the apparent MIPS rating for the program if it is run on the 4-processor system and the sequential part must be completed before any of the remaining

Suppose that each of the 4 processors in a shared memory multi-processor system is rated at 400 MIPS. A program contains a purely sequential part that accounts for 22% of the program’s execution time on a single processor. The remaining code can be partitioned into three independent parts (A, B, and C). Running on a single processor, part A accounts for 30% of the program’s execution time, part B accounts for 18%, and part C accounts for 30%. What is the apparent MIPS rating for the program if it is run on the 4-processor system and the sequential part must be completed before any of the remaining

Name: Suppose that each of the 4 processors in a shared memory multi-process
Uploaded: 2024-03-20T06:51:23.000Z
Channel: Bartleby
Description: Suppose that each of the 4 processors in a shared memory multi-processor system is rated at 400 MIPS. A program contains a purely sequential part that accounts for 22% of the program’s execution time on a single processor. The remaining code can be p

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

See similar textbooks

Similar questions

_____ is a CPU design technique in which instruction execution is divided into multiple stages and different instructions can execute in different stages simultaneously.
Consider a Computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of 6 addressingmodes, and it has 60 computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory AddressGiven that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction.
Computer A has an overall CPI of 1.3 and can be run at a clock rate of 600MHz. Computer B has a CPI of 2.5 and can be run at a clock rate of 750 MHz. We have a particular program we wish to run. When compiled for computer A, this program has exactly 100,000 instructions. How many instructions would the program need to have when compiled for Computer B, in order for the two computers to have exactly the same execution time for this program? Please explain how to solve
Imagine that you have implemented an algorithm in a program which has 40% parallelizable code. Now consider the following two cases assuming that scheduling overhead is ignored: -The program is executed on a single processor. -The program is executed on a parallel system with 4 processors. Compute the speed-up gained in the case where multiple processors are used.
Consider a computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of “6” addressing modes, and it has “50” computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory Address Given that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction
Consider a hypothetical microprocessor generating a 16-bit address (for example, assume that the program counter and the address registers are 16-bits wide) and having a 16-bit data bus. What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”? What is the maximum memory address space that the processor can access directly if it connected to an “8-bit memory”? What architectural features will allow this microprocessor to access a separate I/O spece? If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support? How many 16-bit I/O ports can the microprocessor support? Are the values in d and e the same?
Suppose a program’s 15-th logical instruction (counting starts from zeroth) is at physical address 1234ABDE16 in the RAM. (contents of any logical address fits into any physical address) What is the physical address in the RAM where the program has been loaded? What is the physical address in the RAM of the last instruction of the program if it has 37 logical instructions altogether?
What measures may be taken to ensure that a CPU's processing cycles are not needlessly squandered while it attempts to handle a huge number of instructions all at once? Can you tell me how much the presence or absence of specific elements affects the viability of this plan? Give an example of one of the results they generate.
Assume a program has 20% store and load. When we run this program in a computer, we observe that L1 instruction cache has a hit rate of 98% and L1 data cache has a hit rate of 96%. The L2 cache has a hit rate of 80%. The access time of L1 cache is 2 cycle, and the access time of L2 cache is 40 cycles. If a miss occurs in L2, we have to go to main memory and the penalty is 100 cycles. Assume that the cache uses physical address.a) Without a TLB, what is the AMAT?b) Assume a TLB is built in the cache and its access time is ignored. If the TLB has a 99% hit rate, what is the new AMAT?c) If there is a 0.01% chance that a page fault happens, and the penalty to fetch a page from the disk is 106cycles, what is the new AMAT?
Consider a hypothetical microprocessor generating a 16-bit address (e.g., assume the program counter and the address registers are 16 bits wide) and having a 16-bit data bus. What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”? What is the maximum memory address space that the processor can access directly if it is connected to an “8-bit memory”? What architectural features will allow this microprocessor to access a separate “I/O space”? If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support? How many 16-bit I/O ports? Explain.
Consider a computer running a program that requires 250 seconds, where 70 seconds is spent executing FP instructions, 55 seconds for INT operations, 85 seconds for load/save operations, and 40 seconds for branch instructions. By how much is the time for INT operations reduced if the total time is reduced by 20%?
Assume a primitive time-sharing operating system is running on a computer with 50,000 32-bit words of main memory, with the resident monitor consuming 10,000 of that. When control is to be assigned to an interactive user, the user’s program and data were loaded into the remaining 40,000 words of main memory. A program is always loaded to start at the location of the 10,000th word; this simplified both the monitor and memory management. Assume that there are four interactive users with the following memory requirements, in words: Job1: 10,000, Job2: 30,000, Job3: 1000, Job4: 5,000 Draw the main memory state diagram considering the following: (a) The monitor loads Job1 and transfers control to it. (b) The monitor decides to load Job2 and transfer control to it. (c) Next, the monitor decides to load Job3 and transfer control to it. (d) Next, the monitor decides to load Job1 and transfer control to it. (e) Next, the monitor decides to load Job4 and transfer control…