Suppose you have a RISC machine with a 2 GHz clock (e, the clock ticks 2 billion times per second). This particular computer uses an instructioncache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings:SET reg, inned; 2 clock cyclesLOAD reg.; 3 clock cyclesADD reg, reg ; 2 clock cyclesADD reg, inned; 1 clock cyclesLOOP LabelName; 2 clock cyclesAssume that the following code fragment is used to sum the element of a numeric array.initialize sumSET regi,SET reg2, MAX SIZESET reg), glistProcessArray:initialize loop counterinitialize array poleterLOAD reg4, [reg]regi, regreg), 4ADDADOLOOP ProcessArrayfetch current List elementpodd current List elementmove array pointer to next elementpouto-decrement reg2, jump to more if reg20If the initialization code has already executed (i.e. the SET instructions have already finished execution) how many array elements can be processed in4.2 milliseconds (ms)? Round your answer to the nearest integer. Recall that 1 ms -0.001 seconds. Also assume that there are no physical memorylimitations, implying that the array can be as large as desired.

Name: Suppose you have a RISC machine with a 2 GHz clock (e, the clock tick
Uploaded: 2024-03-20T06:51:23.000Z
Channel: Bartleby
Description: Suppose you have a RISC machine with a 2 GHz clock (e, the clock ticks 2 billion times per second). This particular computer uses an instructioncache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simpl

Answered: Image /qna-images/answer/68ac06bd-2ad8-4eb2-9876-84967dbed24a.jpg

Engineering

Computer Science

Suppose you have a RISC machine with a 2 GHz clock (ie, the clock ticks 2 billion times per second). This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings: SET reg, inned; 2 clock cycles LOAD reg. ; 3 clock cycles ADD reg, reg; 2 clock cycles ADD reg, inned; 1 clock cycles LOOP LabelName; 2 clock cycles Assume that the following code fragment is used to sum the element of a numeric array. SET regi, SET reg2, MAX SIZE SET reg), glist _ProcessArray: LOAD reg4, [reg3) regi, reg reg3, 4 ADD ADD LOOP ProcessArray Initialize sum initialize loop counter initialize array pointer fetch current List element odd current List element move array pointer to next element pouto-decrement reg2, jump to more if reg20 If the initialization code has already executed (i.e. the SET instructions have already finished execution) how many array elements can be processed 4.2 milliseconds (ms)? Round your answer to the nearest integer. Recall that 1 ms -0.001 seconds. Also assume that there are no physical memory limitations, implying that the array can be as large as desired.

Suppose you have a RISC machine with a 2 GHz clock (ie, the clock ticks 2 billion times per second). This particular computer uses an instruction cache, a data cache, an operand fetch unit, and an operand store unit. The instruction set includes simple instructions with the following timings: SET reg, inned; 2 clock cycles LOAD reg. ; 3 clock cycles ADD reg, reg; 2 clock cycles ADD reg, inned; 1 clock cycles LOOP LabelName; 2 clock cycles Assume that the following code fragment is used to sum the element of a numeric array. SET regi, SET reg2, MAX SIZE SET reg), glist _ProcessArray: LOAD reg4, [reg3) regi, reg reg3, 4 ADD ADD LOOP ProcessArray Initialize sum initialize loop counter initialize array pointer fetch current List element odd current List element move array pointer to next element pouto-decrement reg2, jump to more if reg20 If the initialization code has already executed (i.e. the SET instructions have already finished execution) how many array elements can be processed 4.2 milliseconds (ms)? Round your answer to the nearest integer. Recall that 1 ms -0.001 seconds. Also assume that there are no physical memory limitations, implying that the array can be as large as desired.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter5: Data Storage Technology

Section: Chapter Questions

Problem 2PE

See similar textbooks

Similar questions

_____ is a CPU design technique in which instruction execution is divided into multiple stages and different instructions can execute in different stages simultaneously.
A(n) ________________ instruction always alters the instruction execution sequence. A(n) ______________ instruction alters the instruction execution sequence only if a specified Condition is true.
Most Intel CPUs use the __________, in which each memory address is represented by two integers.
Suppose that a RISC machine uses five register windows.Q) How deep can the procedure calls go before registers must be saved in memory? (That is, what is the maximum number of “active” procedure calls that can be made before we need to save any registers in memory?
Suppose an instruction takes four cycles to execute in a nonpipelined CPU: one cycle to fetch the instruction, one cycle to decode the instruction, one cycle to perform the ALU operation, and one cycle to store the result. In a CPU with a four-stage pipeline, that instruction still takes four cycles to execute, so how can we say the pipeline speeds up the execution of the program?
Suppose you have a computer that does instruction processing in anatomic way, with a clock cycle of 7ns and one instruction executioncompleted every cycle.You now split the processing into the five stages of the RISC pipeline,and you get required processing times of• IF: 1ns• ID: 1.5ns• EX: 1ns• MEM: 2ns• WB: 1.5nsYou now have added 0.1ns of delay between each of these stages. What’s the clock cycle time of this 5-stage pipelined machine?
Interface an 80286 microprocessor with total memory size 128KB using RAM chip size of 16KB. Show the detail of your drawing.
Suppose a RISC machine uses overlapping register windows for passing parameters between procedures. The machine has 298 registers. Each register window has 32 registers, of which 10 are global variables and 10 are local variables.Q) By how much would the current window pointer (CWP) be incremented at each procedure call?
Suppose a RISC machine uses overlapping register windows for passing parameters between procedures. The machine has 298 registers. Each register window has 32 registers, of which 10 are global variables and 10 are local variables.Q) How many registers would be available for use by output parameters?
In a computer instruction format, the instruction length is 16 bits, and the size of an address field is 4 Is it possible to have: 15 instructions with 3 addresses, 14 instructions with 2 addresses, 31 instructions with one address, and 16 instructions with zero addresses, using this format? Justify your answer.
A complete 6-stage non-pipelined 16-bit CPU architecture include 6 components: a register file, a decoder, an ALU, a control unit, a program counter, and ram/memory. Brief overview: opcode is 4 bits 14 different instructions implemented 8 general purpose registers RRR-type instructions are the largest, and take up 9 bits in register addresses 1 bit is a condition bit 2 bits unused simulated clock runs at a 10ns period or 100Mhz simulated memory is 512 bytes Referring to the 3 components as in the picture, namely the File Register, Decoder and ALU, you are required to describe how the three components operate.
Single instruction computer (SIC) has only one instruction that for all operations our MIPS does. The instruction has the following format. sbn a, b, c # Mems[a]=Mem[a]- Mem[b]; if (Mem[a]<0) go to PC+c For example, here is the program to copy a number from location a to location b: Start: sbn temp, temp, 1 sbn temp, a, 1 sbn b, b, 1 sbn b, temp, 1 So build SIC program to add a and b, leaving the result in a and leaving b unmodified.