Answered: A complete 6-stage non-pipelined 16-bit…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Question

A complete 6-stage non-pipelined 16-bit CPU architecture include 6 components: a register file, a decoder, an ALU, a control unit, a program counter, and ram/memory.

Brief overview:

opcode is 4 bits
14 different instructions implemented
8 general purpose registers
RRR-type instructions are the largest, and take up 9 bits in register addresses
1 bit is a condition bit
2 bits unused
simulated clock runs at a 10ns period or 100Mhz
simulated memory is 512 bytes

Referring to the 3 components as in the picture, namely the File Register, Decoder and ALU, you are required to describe how the three components operate.

ALU:
clk in
enable_in
alu_op_in
pc_in
rM_data_in,
rN_data_in
imm_data_in
rD_write_enable_in
16
result_out
branch out
rD write enable_out
16
16
ALU
16
1

Register file:
clk_in
enable in
write_enable_in
16
rM_data_out
REGISTER FILE
16
rN_data_out
rD_data_in
sel_rM_in
sel rN in
| 16
3
ro-r7 x 16 bits
3
sel_rD_in
3
Decoder:
clk_in
enable in
• alu_op_out
imm data out
instruction_in
16
write_enable_out
sel_rM_out
DECODER
sel_rN_out
3
sel_rD_out

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