Question

Suppose you have a computer that does instruction processing in an
atomic way, with a clock cycle of 7ns and one instruction execution
completed every cycle.
You now split the processing into the five stages of the RISC pipeline,
and you get required processing times of
• IF: 1ns
• ID: 1.5ns
• EX: 1ns
• MEM: 2ns
• WB: 1.5ns
You now have added 0.1ns of delay between each of these stages.

What’s the clock cycle time of this 5-stage pipelined machine?

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