Task #1: Describe a 4-bit adder. The output of the adder is displayed on two 7-segment displays (Why?). You will make use of the BCH (Binary-Coded Hexadecimal) converter to display the output (i.e. through module instantiation). What should be the bit width of the output signal SUM? D1 Adder SUM D2 1. Create a new Quartus II project. Write a Verilog module that describes the 4-bit adder circuits shown above. Make use of the BCH converter module through module instantiation.

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Task #1: Describe a 4-bit adder. The output of the adder is displayed on two 7-segment displays (Why?). You
will make use of the BCH (Binary-Coded Hexadecimal) converter to display the output (i.e. through module
instantiation). What should be the bit width of the output signal SUM?
D1
Adder
SUM
D2
1. Create a new Quartus II project. Write a Verilog module that describes the 4-bit adder circuits shown
above. Make use of the BCH converter module through module instantiation.
2. Use the document “DE1-SoC User Manual" to connect the input ports D1 & D2 to ON/OFF switches,
and the output SUM to two 7-segment displays.
3. Program the platform FPGA and validate the design. Show your work to the lab instructor.
Homework: Simulate the design using ModelSim. Submit a compressed file that contains the circuit, tester,
and testbench. Additionally, embed simulation waveforms to the report that discusses the results.
Transcribed Image Text:Task #1: Describe a 4-bit adder. The output of the adder is displayed on two 7-segment displays (Why?). You will make use of the BCH (Binary-Coded Hexadecimal) converter to display the output (i.e. through module instantiation). What should be the bit width of the output signal SUM? D1 Adder SUM D2 1. Create a new Quartus II project. Write a Verilog module that describes the 4-bit adder circuits shown above. Make use of the BCH converter module through module instantiation. 2. Use the document “DE1-SoC User Manual" to connect the input ports D1 & D2 to ON/OFF switches, and the output SUM to two 7-segment displays. 3. Program the platform FPGA and validate the design. Show your work to the lab instructor. Homework: Simulate the design using ModelSim. Submit a compressed file that contains the circuit, tester, and testbench. Additionally, embed simulation waveforms to the report that discusses the results.
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