Subject: Operating Systems The memory system has L1 and L2 cache, the translation lookaside buffer (TLB), and a pagetable (PT). When the data at an address is needed, the memory management unit (MMU)takes the following steps.4.1 MMU simultaneously looks up the data in L1 and L2 cache.4.1.1 If the data is in L1 cache, MMU spends no time for this step. This happens with aprobability of 0.9.4.1.2 The data is in L2 cache. This takes X units of time and happens with a probabilityof 0.09. 4.1.3 If the data is in L1 or L2 cache, Steps 4.2, 4.3, and 4.4 are skipped. If the data isnot in either L1 or L2 cache, MMU proceeds to Step 3.2 with a probability of 0.01.4.2 MMU simultaneously queries the TLB and the PT. Assume that Z> Y > 0.4.2.1 MMU gets the page frame number from the TLB, which takes Y units of time witha probability of 0.98.4.2.2 MMU looks up the page frame number from the PT, which takes Z units of timewith a probability of 0.02.4.2.3 If Step 4.2.1 is successful, Step 4.2.2 is aborted. Regardless which step is successful,now MMU has the page frame number and it continues to Step 4.3.4.3 If a page fault occurs, the OS kernel needs U units of time to bring the page from diskto RAM. This happens with a probability of 0.0001 - there is no page fault with aprobability of 0.9999. At this point, the page we need is in RAM.4.4 Finally, MMU delivers the data from RAM to L1 cache, taking V units of time.What is the average memory access time?

Name: Subject: Operating Systems The memory system has L1 and L2 cache, the
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Description: Subject: Operating Systems The memory system has L1 and L2 cache, the translation lookaside buffer (TLB), and a pagetable (PT). When the data at an address is needed, the memory management unit (MMU)takes the following steps.4.1 MMU simultaneously lo

L1 and L2 which refers to the levels of cache memory in a computer. If the computer that has th…

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The memory system has L1 and L2 cache, the translation lookaside buffer (TLB), and a page table (PT). When the data at an address is needed, the memory management unit (MMU) takes the following steps. 4.1 MMU simultaneously looks up the data in L1 and L2 cache. 4.1.1 If the data is in L1 cache, MMU spends no time for this step. This happens with a probability of 00

The memory system has L1 and L2 cache, the translation lookaside buffer (TLB), and a page table (PT). When the data at an address is needed, the memory management unit (MMU) takes the following steps. 4.1 MMU simultaneously looks up the data in L1 and L2 cache. 4.1.1 If the data is in L1 cache, MMU spends no time for this step. This happens with a probability of 00

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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