Topic: 4 bit 2’s Complement Multiplier instruction :Build a 4 Bit UNSIGNED Multiplier as a subcircuit and write truth table for the circuit use AND gates,full and half adders
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Topic:
4 bit 2’s Complement Multiplier
instruction :Build a 4 Bit UNSIGNED Multiplier as a subcircuit and write truth table
for the circuit use AND gates,full and half adders
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- Design 2-bit synchronous counter that counts 0, 1, 2, 3 in succession. Draw the given counter’s counting table (state diagram) in binary and decimal form below . Indicate the transitions.1. Using ic chip such as 74LS283 find the following: Part 1: Results of 10 4-bit Additions Part 1: Circuit Diagram of the IC chip Part 2: Results of 5 2-bit additions, and 5 2-bit subtractions Part 2: Circuit Diagram of the 2-bit Adder/SubtractorDesign the complete data path for “sub $S4, $S1, $S2” instruction for the MIPS architecture.
- Describe LDS BX, LOC instruction operator.Explain the concept of ALU (Arithmetic Logic Unit) and its role in computer architecture.NAND2TETRIS HARDWARE SIMULATOR (HARDWARE DESCRIPTION LANGUAGE (HDL)) ,USING SKELETON PROGRAM PROVIDED AND USING PREDIFINED GATES ATTACHED. CHIP HiLoMux { IN in[8], sel; OUT out[4]; PARTS: } Implement HiLoMux - This has one 8-bit input bus, in, and one 4-bit output bus, out. Alsopresent is a sel input, which is used to select what appears on out. Ifsel is false, then out should contain the lower 4-bits of in (i.e. in[0],in[1], in[2], in[3]). If sel is true, then out should contain theupper 4-bits of in (i.e. in[4] mapped to out[0], in[5], mapped toout[1], etc.).
- Design Problem No. 1 – Up - Down Counter with Enable Design, construct, and simulate a 2-bit counter that counts up and down. An enable input E determines whether the counter is on or off. If E = 0, the counter is disabled and remains at its present count even though clock pulse is applied to the flip-flops. If E = 1, the counter is enabled and a second input, x, determines the count direction. If x = 1, the circuit counts up with the sequence S1, S2, S3, S4, and count repeats. If x = 0, the circuit counts down with the sequence S4, S3, S2, S1, and the count repeats. Do not use E to disable the clock. Design the sequential circuit with E and x inputs. Implement the logic diagram with JK flip-flops.2. 7.4.8 Circuit analysis. Give the number of switches in each of the following. a. Register bit b. Memory bit c. 8-bit register d. Memory with sixteen 8-bit words e. Clock Count every switch (for example, a 2-way AND gate has four switches).(Logic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)* Decoder 74hc138Or you can use 74HCxx versions.) Task 3: Design a Binary Ripple Carry Adder for 5+3 summation in BCDcoding system. Draw the the circuit diagram by using FullAdder Blocks. Simulate the circuit.
- 1. Design a SINGLE 4-bit ALU that performs Arithmetic (add, subtraction), and Logicoperations (AND, OR). The following control signals are to be considered:• A/S: add/subtract (0:add, 1:subtract)• A/O: and/or (0:and, 1:or)• A/L: arithmetic/Logic (0:arithmetic, 1:logic)• R/W: read/write signal (0:read, 1:write) The details of each control signal (Unit) are as follows. Unit 1 (A/S) - Design a 4-bit adder/subtractor that accepts two 4-bits numbers, A andB, and either add them up (A + B) or subtract them (A – B) depending on a controlsignal A/S (when the control signal is 0 perform ADD, otherwise if the signal is 1 thenperform SUB). The result will be stored in C. Unit 2 (A/O) - Design a 4-bit AND/OR unit that accepts two 4-bits numbers, A and B,and either AND them or OR them depending on a control signal A/O (when the controlsignal is 0 perform AND, otherwise if the signal is 1 then perform OR – bitwise logicaloperation). The result will be stored in C. Unit 3 (A/L) - Design a 4-bit ALU…Computer Science A computer uses a memory of 64K words with 16 bits in each word.It has the following registers: PC, AR, TR, AC, DR and IRA memory-reference instruction consists of two words: an 16-bit operation-code(one word) and an address field (in the next word).a-List the sequence of microoperations for fetching a memory reference instructionand then placing the operand in DR. Start from timing signal To.b-Design the logic control gates arrangement to perform the fetch instructions.1. Design a 4-bit ALU that performs Arithmetic (add, subtraction), and Logicoperations (AND, OR). The following control signals are to be considered:• A/S: add/subtract (0:add, 1:subtract)• A/O: and/or (0:and, 1:or)• A/L: arithmetic/Logic (0:arithmetic, 1:logic)• R/W: read/write signal (0:read, 1:write) The details of each control signal (Unit) are as follows.Unit 1 (A/S) - Design a 4-bit adder/subtractor that accepts two 4-bits numbers, A andB, and either add them up (A + B) or subtract them (A – B) depending on a controlsignal A/S (when the control signal is 0 perform ADD, otherwise if the signal is 1 thenperform SUB). The result will be stored in C.Unit 2 (A/O) - Design a 4-bit AND/OR unit that accepts two 4-bits numbers, A and B,and either AND them or OR them depending on a control signal A/O (when the controlsignal is 0 perform AND, otherwise if the signal is 1 then perform OR – bitwise logicaloperation). The result will be stored in C.Unit 3 (A/L) - Design a 4-bit ALU using Unit…