Using Verilog language design and verify a FP adder using single precision IEEE 754 format. •The inputs are assumed to be normalized and your design should generate a normalized output. •The adder can be of any type , and please provide a test bench because no one provided the test bench before , and please please test the code on EdaPlayground.com because i'm only using an online simulator , and thank you    No hand written and fast answer with explanation

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