variable v_Count : natural range 0 to 5 := 0; begin if rising_ edge(i_clk) then v_Count := v_Count + 1; r_Var_Copy1 <= v_Count; if v Count = 5 then %3D
variable v_Count : natural range 0 to 5 := 0; begin if rising_ edge(i_clk) then v_Count := v_Count + 1; r_Var_Copy1 <= v_Count; if v Count = 5 then %3D
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question
![Explain what the following VHDL code does. [20 marks]
EX_VAR : process (i_clk)
variable v_Count : natural range 0 to 5 := 0;
begin
if rising_edge(i_clk) then
v_Count := v_Count + 1;
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r_Var_Copy1 <= v_Count;
27
if v_Count = 5 then
r_Done <= '1';
v_Count := 0;
else
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%3D
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r_Done <= '0';
end if;
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r_Var_Copy2 <= v_Count;
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end if;
end process EXx_VAR;
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o done <= r_Done;
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end rtl;](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F79c9bbfe-ee55-4e4a-8638-19dc1f2934f8%2F4159a205-1f27-4853-bc05-e6ff41638b1c%2Fvh6ahmz_processed.jpeg&w=3840&q=75)
Transcribed Image Text:Explain what the following VHDL code does. [20 marks]
EX_VAR : process (i_clk)
variable v_Count : natural range 0 to 5 := 0;
begin
if rising_edge(i_clk) then
v_Count := v_Count + 1;
20
21
22
23
24
25
26
r_Var_Copy1 <= v_Count;
27
if v_Count = 5 then
r_Done <= '1';
v_Count := 0;
else
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%3D
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r_Done <= '0';
end if;
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r_Var_Copy2 <= v_Count;
36
end if;
end process EXx_VAR;
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40
o done <= r_Done;
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42
end rtl;
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