Verilog module testbench2 (); reg a, b, c; wire y; // instantiate device under test sillyfunction dut (a, b, c, y); // apply inputs one at a time // checking results initial begin 0; #10; = 0; b = 0; c = if (y !== 1) $display(“000 failed."); a C 1; #10; 0) $display(“001 failed."); 1; c = 0; if (y !== 0) $display(“010 failed."); if (y !=: b #10; C 1; #10; if (y !== 0) $display(“011 failed."); 1; b = 0; c = 0; #10; if (y !== 1) $display(“100 failed."); c = 1; a = 3%3D #10; 1) $display(“101 failed."); #10; if (y !== 1; c = 0; if (y !== 0) $display(“110 failed."); c = 1; if (y !== b = #10; 0) $display(“111 failed."); end endmodule
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