We would like to expand the RISC-V register file to 128 registers and expand the instruction set to contain four times as many instructions. (a) How would this affect the size of each of the bit fields in the R-type instructions? (b) How could each of the two proposed changes along decrease the size of a RISC-V assembly program? On the other hand, how could the two proposed changes together increase the size of an RISC-V assembly program?
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- For the MIPS assembly instructions below, what is thecorresponding C statement? Assume that the variables f, g, h, i, and j areassigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume thatthe base address of the arrays A and B are in registers $s6 and $s7,respectively. Note: for each line of MIPS code below, write the respective Ccode. After that, write the corresponding C code for the MIPS.sll $t0, $s0, 2add $t0, $s6sll $t1, $s1, 2 add $t1, $s7, $t1lw $s0, 0($t0)addi $t2, $t0, 4lw $t0, 0($t2)add $t0, $t0, $s0sw $t0, 0($t1)A recent paper proposed eliminating paging and using segmentation instead.Their reasoning was that memories can be made large enough to avoid usingvirtual memory in most cases. Suppose we adopt this philosophy and requirethat all memory references refer to a segment descriptor. Give a design forsuch a descriptor. What changes would you make to the RISC-V instructionset and architecture?I have this problem from my textbook that I do not understand, despite re-reading the section on segmentation and paging. "The IBM system/370 architecture uses a two-level memory structure and refers to the two levels as segments and pages, although the segmentation approach lacks many of the features described in Chapter 8. For the basic 370 architecture, the page size may be either 2 KB or 4 KB, and the segment size is fixed at either 64 KB or 1 MB. For the 370/XA and 370/ESA architectures, the page size is 4 KB and the segment size is 1 MB. What advantages of segmentation does this scheme lack? What is the benefit of segmentation for the 370?"Can you help me undertand what they are looking for in this explanation?
- Please look at the whole document and show all work and steps. Please solve and show work. What is the corresponding MIPS assembly code for the following C statement? Assume that the variables f, g, h, i, and j are assigned to register $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. B[8] = A[i−j] Translate the following C code to MIPS. Assume that the variables f, g, h, i, and j are assigned to register $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Assume that the elements of the arrays A and B are 8-byte words: B[8] = A[i] + A[j] Assume that registers $s0 and $s1 hold the values 0x80000000 and 0xD0000000, respectively. What is the value of $t0 for the following assembly code? add $t0, $s0, $s1 Is the result in $t0 the desired result, or has there been an overflow? For the contents of registers $s0…For the MIPS assembly instructions below, what is the corresponding C statement?Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and$s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. sll $t1, $s1, 2add $t1, $t1, $s6lw $t1, 0($t1)sub $t0, $s3, $s4sll $t0, $t0, 2add $t0, $t0, $s7lw $t0, 0($t0)add $t1, $t1, $t0sll $t0, $s0, 2add $t0, $t0, $s7sw $t1, 0($t0)Please solve and show all work. Thank you. What is the corresponding MIPS assembly code for the following C statement? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Assume that the elements of the arrays A and B are 4-byte words: f = g + (h − 5); B[8] = A[i] + A[j+1];
- Consider a simple read-only memory (ROM) unit with 2-bit addressand 2-bit data buses.Draw the internal architecture of such a ROM unit includingtransistors, address and data signals, and the row decoder.? I have attached the answer to the question, but I am confused by it, if you could explain every step including how many transistors to use, where to place them and the basic procedure which could be used with other similar questions that would be helpful, do not copy and paste off chatgptWhich kind of parallelism at the programme level, data or control, does the SIMD instruction set work best with? Which kind of parallelism at the programme level works best with MIMD?Which kind of parallelism at the programme level, data or control, does the SIMD instruction set work best with? Which kind of mirroring at the level of the plan does MIND do best?
- (ASM) For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. B[f] = A[(i-h)+j] + g;I have a little bit problem with my late quiz for computer architecture, I get the answer from my lecturer but I still don't feel fully understand, can I ask for some help: In a computer system, the memory has 32 blocks and the cache has 8 blocks. Assume there is only one word per block with 4 bytes in one word. The reference sequence in terms of word location is 0, 2, 4, 10, 5, 12, 8, 18, 13. If the cache is direct-mapped, how many misses do we have if the cache is initially empty? Can you give the hit or miss for each reference?We want to build a byte organized main memory of 8 GB for a 32-bit CPU architecture composed ofbyte organized memory modules of 30-bit address and 8-bit data buses each.a) Draw the interface of the main memory by clearly indicating the widths of the buses.b) How many memory modules would be necessary to build the memory system?c) Design the main memory internal organization built out of the above memory modules (usemultiplexers and/or decoders as needed) by clearly indicating the widths of the used bussesd) Can we use this memory system as RAM for the CPU in Problem 1? Explain your answer.