What is load Balancing? What are the two approaches of Load Balancing Write about Algorithm Evaluation( How do we select a CPU-Scheduling algorithm for a particular System) Write about Test and Set Instruction and about Swap Instruction How to avoid deadlock by using RAG Algorithm and Bankers Algorithm

What is load Balancing? What are the two approaches of Load Balancing Write about Algorithm Evaluation( How do we select a CPU-Scheduling algorithm for a particular System) Write about Test and Set Instruction and about Swap Instruction How to avoid deadlock by using RAG Algorithm and Bankers Algorithm

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 10RQ: How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency...

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If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
What exactly is load balancing? What are the two Load Balancing approaches? Write a paper on Algorithm Evaluation ( How do we select a CPU-Scheduling algorithm for a particular System) Write about the Test and Set Instructions as well as the Swap Instructions. How to Avoid Deadlock Using RAG and Bankers Algorithms How can you get out of a deadlock? Describe the methods of recuperation.
10. Q1 : What is an atomic instruction? Show that if the wait operation is not executed atomically, then mutual exclusion may be violated Q2: What is spinlock? Discuss the advantage and disadvantage of using spinlock. Why do you think Solaris, Linux, and Windows 2000 use spinlocks as a synchronization mechanism only on multiprocessor systems and not on single- processor systems?
How would it be advantageous to prioritize the I/O queue above the process execution queue? What will happen if the I/O is interrupted is anyone's guess. Indications are conflicting as to how this could effect the maximum burst rate of the CPU. I'm confused as to the nature of your question.
How can we minimize the CPU time wasted by concurrently executing several instructions? Which steps in this procedure are the most crucial, and why? What impact do they have?
In the Compare&Swap instruction, why must the instruction execute atomically? Write about: Busy waiting - is undesirable because it’s inefficient Potential starving of a process Deadlock - low priority process and high priority process are stuck Compare&Swap: // critical section based on // compare_and_swap instruction Shared variable x=0 while (true) { while (compare_and_swap(x, 0, 1) == 1) // do nothing // critical section code here x = 0; // remaining code… } // instruction logic int compare_and_swap(int *word, int testval, int newval) { int oldval; oldval = *word; if (oldval == testval) *word = newval; return oldval; }
How does speculative execution relate to instruction pipelining, and what are the potential security vulnerabilities associated with speculative execution in modern CPUs?
Assume two secondary memory processes exist. In light of phase 1, one priority is higher than the other. Only one process can fit in main memory. How does the CPU work on it? Can you explain the whole CPU mechanism?
Because of this, the CPU suspends any currently executing processes until the interrupt has been resolved. Interrupt service is the term used to describe this. What is the rationale for halting the procedure that is presently in progress? Isn't it possible, as an alternative, to just finish the presently operating operation and deal with the interruption afterward?
Describe the concept of "memory latency" and its impact on CPU performance. How can memory access times be minimized?
Is it still feasible to accomplish pipelined execution even if the time it takes to execute pipeline instructions is not balanced? Where can you perceive the inefficiencies in this situation?
What are the two main steps involved in an instruction cycle? If the CPU needs to be alerted by the keyboard and the mouse at the same time, How the CPU will handle interrupts from the keyboard and the mouse at the same time? There are two ways... Which cache mapping does not need a replacement algorithm? Which cache mapping scheme has the largest TAG? Only a microprocessor is accessing the memory via cache i.e. no other device is reading from memory. Which cache write the policy will you use and why.