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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?How many total bits are required for a direct-mapped cache with 16 KiB of data and 4-word blocks, assuming a 32-bit address?Suppose the cache access time is 20ns, main memory access time is 100ns, and the cache hit rate is 90%. Assuming parallel (overlapped) access, what is the average access time for the processor to access an item?
- Suppose we have a processor with a base CPI of 2.0 assuming all references hit in the pnmary cache and a clock rate of 1000 MHz. The main memory access time is 100 ns. Suppose the miss rate per instruction is 5%. What is the revised CPI? How much taster will the machine run it we put a secondary cache (with 20-ns access time) that reduces the miss rate to memory to 2%A 64 KB 2-way set-associative cache is byte-addressable and contains 32 byte lines. Memory addresses are 64-bit wide.How wide are the tags in this cache?A computer has a 256 KB, K-way set associative write-back data cache with block size of 32 B. The address sent to the cache controller by the processor is of 32 bits. In addition to the address tag, each cache tag directory contains 2 valid bits and 1 modified bit. If 16 bits are used to address tag. What is the minimum value of K?
- A two way set associative cache can host 32 KB (Kilobyte) of memory data with 16-word block. The memory system has 32 bits address bus. How many total bits does this cache have. (include 1 validation bit for each cache line, assume each word is one byte long).I am confused A memory system has a 32 KB byte-addressable main memory and a 1 KBcache where each block contains 16 bytes. Determine the format of the address in each of thecache organizations. In each case list the address fields and the width of each field.a) Direct-mapped cacheb) Fully-associative cachec) 4-way set-associative cacheSuppose a computer using fully associative cache has 216 bytes of byte-addressable main memory and a cache of 64 blocks, where each cache block contains 32 bytes.Q.) To which cache block will the memory address 0xF8C9 map?
- Suppose a direct-mapped cache uses a 16K L1 memory and a 256K L2 memory. How many of the L2 address bits will L1 use as tag bits?Consider a system with 4GB of memory address space. Assuming a write-back policy and block size of 32 bytes, find the space overhead when it uses a (a) 64 KB direct mapped cache(b) fully associative cache (c) eight-way set-associative cacheA 1 GByte RAM with 64 word/line is mapped to an 8 kLine Cache with Associative Mapping. What will the address look like?