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You are designing the memory hierarchy for a new processor. The access latency of main memory is 200 cycles. You have the following choices for the L2 design: ● ● ● 2MB, 16-way set-associative. Hit time = 30 cycles. %miss = 1% 1MB, 8-way set associative. Hit time = 20 cycles. %miss = 5% 512KB, 4-way set associative. Hit time = 15 cycles. %miss = 10% And the following choices for L1 design: 64KB, 8-way set associative. Hit time = 2 cycles. %miss = 4% 32KB, 4-way set associative. Hit Time = 1 cycle. %miss = 5% Question: Which cache design would you choose and why?

You are designing the memory hierarchy for a new processor. The access latency of main memory is 200 cycles. You have the following choices for the L2 design: ● ● ● 2MB, 16-way set-associative. Hit time = 30 cycles. %miss = 1% 1MB, 8-way set associative. Hit time = 20 cycles. %miss = 5% 512KB, 4-way set associative. Hit time = 15 cycles. %miss = 10% And the following choices for L1 design: 64KB, 8-way set associative. Hit time = 2 cycles. %miss = 4% 32KB, 4-way set associative. Hit Time = 1 cycle. %miss = 5% Question: Which cache design would you choose and why?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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You are designing the memory hierarchy for a new processor. The access latency of main memory is 200 cycles. You have the following choices for the L2 design: ● 2MB, 16-way set-associative. Hit time = 30 cycles. %miss = 1% 1MB, 8-way set associative. Hit time = 20 cycles. %miss = 5% 512KB, 4-way set associative. Hit time = 15 cycles. %miss = 10% ● And the following choices for L1 design: 64KB, 8-way set associative. Hit time = 2 cycles. %miss = 4% 32KB, 4-way set associative. Hit Time = 1 cycle. %miss = 5% Question: Which cache design would you choose and why? * ● Please solve correctly and explain completely. Thank you.
Transcribed Image Text:You are designing the memory hierarchy for a new processor. The access latency of main memory is 200 cycles. You have the following choices for the L2 design: ● 2MB, 16-way set-associative. Hit time = 30 cycles. %miss = 1% 1MB, 8-way set associative. Hit time = 20 cycles. %miss = 5% 512KB, 4-way set associative. Hit time = 15 cycles. %miss = 10% ● And the following choices for L1 design: 64KB, 8-way set associative. Hit time = 2 cycles. %miss = 4% 32KB, 4-way set associative. Hit Time = 1 cycle. %miss = 5% Question: Which cache design would you choose and why? * ● Please solve correctly and explain completely. Thank you.
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