Performance Improvement Of Full Adder Using H Cmos Logic Essay

1959 Words8 Pages
Performance Improvement of Full Adder using H-CMOS Logic Imran Mehmood* and Muhammad Aqueel Ashraf Department of Electronics, Quaid-i-Azam University Islamabad, Pakistan. *Email: imran_kanjoo@yahoo.com Abstract— In this research work we present hybrid CMOS (H-CMOS) logic style for the performance improvement of one bit full Adder cell. This structure provides better implementation of for the proposed full Adder in terms of delay and compared to its counterpart power delay product. It is expected to that the propagation delay of the proposed structure of the full Adder provides more than 22 percent less compared to the next fastest Adder available. HSpice simulations using 65nm technology with a power supply of 1.2V was utilized to evaluate the performance of the circuits. Keywords— full Adder, high-performance, high-speed, hybrid-CMOS, propagation delay. INTRODUCTION Most of the VLSI applications, such as digital signal processing, image and video processing, and digital filter design, widely use arithmetic operations. Addition, subtraction and multiplication are examples of the most commonly used operations. The 1-bit full Adder cell is the building block of these units. Hence, improving its performance is critical for improving the overall unit performance. The most important performance parameters for a generic VLSI system are power consumption, speed, and chip area. Several logic styles have been used in the past to design full Adder cells. Each logic style has

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