Solve this question on memory hierarchies in computer structures (Refer to the screenshot); 1) Assume that a computer has 32 bit addresses. Each block stores 16 words. A direct-mapped cache has 256 blocks. In which block (line) of the cache would we look for eachof the following addresses? The addresses are given in hexadecimal for convenience.a)1A2BC012b) FFFF00FF12345678C109D532

For a direct-mapped cache, the address is typically divided into three parts:TagIndexBlock offset…

Answered: 1) Assume that a computer has 32 bit…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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1. For a direct-mapped cache design with a 32-bit address, the following bits of address are used to access the cache. Tag Index Offset 31-14 13-7 6-0 a. What is the cache block size (in words)? b. How many entries does this cache have? c. What is the ratio between total bits required for such a cache implementation over the data storage bits?
Assume a fully associative cache of size 32kiB and block size of 64Bytes. Determine: i) the number of cache blocks. ii) the number of bits required for the cache block offset. iii) the number of Tag bits
Assume that there is a direct mapped cache memory. Assume it has block size B capacity of N words. The length of the TAG field is 10 bits. What will be the length of the TAG field (in bits) if the cache unit is now designed as a 16-way set-associative cache?.
Assume we have a computer with 512 blocks of cache memory with a total capacity of 128K bits. Answer the following questions knowing that the computer operates in a word addressable mode and that the format of the memory address as perceived by the Fully associative cache scheme is as shown below: Cache Format with Full Associativity 19 5 1- How many words are in each cache block? 2- How big are the letters in each word? 3- How large is the primary memory? 4- What is the total number of blocks in main memory? 5- Draw the memory address format as observed by the Direct Mapped Cache technique, including the fields and their sizes.
For a direct-mapped cache design with a 32-bit address, the following bits of the address areused to access the cache.Tag Index Offset31–10 9–6 5–0a– What is the cache block size (in words)? b – How many entries does the cache have? c – What is the ratio between total bits required for such a cache implementation overthe data storage bits?
3) Assume that there is a cache with 4 blocks and the block size is 1 byte (in total only 4B cache). The cache is initially empty. For two different configurations of the cache; direct-mapped and 2-way set associative, given memory addresses are accessed in the given order. Write if given addresses are hit or miss in the cache. address: 3 - 11 - 0 - 3 - 11
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88
Determine which bits in a 32-bit address are used for selecting the byte (B), selecting the word (W), indexing the cache (I), and the cache tag (T), for each of the following caches: C. 4096-line, 4-way set-associative, write back, 64 byte line
Assume that we have a computer with a cache memory of 512 blocks with a total size of 128K bits. Knowing that the computer uses a word addressable mode and the format of the memory address as seen by the Fully associative cache scheme is as shown below, answer the below questions: Fully Associative Cache Format 19 5 1- How many words do we have in each cache block? 2- What is the size of each word? 3- What is the size of the main memory? 4- How many blocks are there in the main memory? 5- Draw the format of the memory address as seen by the Direct Mapped Cache scheme, showing the fields as well as their sizes.
Assume that we have a computer with a cache memory of 512blocks with a total size of 128K bits. Knowing that the computer uses a word addressable mode and the format of the memory address as seen by the Fully associative cache scheme is as shown below, answer the below questions: Fully Associative Cache Format 1- How many words do we have in each cache block? 2- What is the size of each word? 3- What is the size of the main memory? 4- How many blocks are there in the main memory? 5- Draw the format of the memory address as seen by the Direct Mapped Cache scheme, showing the fields as well as their sizes.
Determine which bits in a 32-bit address are used for selecting the byte (B), selecting the word (W), indexing the cache (I), and the cache tag (T), for each of the following caches: B. 256-line, fully-associative, write back, 16 byte line
Assume a cache system has been designed such that cach block contains 4 words and the cache has 1024 lines, the cache can store up 10 1024 blocks. What line of the cache is supposed 10 hold the block that contains the word from the twenty-bit address JA456:? In addition, what is the tag number that will be stored with the block?

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1) Assume that a computer has 32 bit addresses. Each block stores 16 words. A direct- mapped cache has 256 blocks. In which block (line) of the cache would we look for each of the following addresses? The addresses are given in hexadecimal for convenience. a) 1A2BC012 b) FFFF00FF 12345678 C109D532