1. Assume data block can hold 512 Bytes and iNode has 10 direct pointers. 11 th point is a single indirect and 12th pointer is a double indirect. There are 12 pointers altogether. Assume address block can hold 12 addresses. Assume the iNode is already in memory. a) Explain how 512*5 Byte can be accessed? b) Explain how 512*15 Byte can be accessed? c) How big file canbe addresse by this l-node? Show your work.
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- CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers: (a) How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate (b) Repeat the above for the index field. (c) Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.Suppose you experience a cache miss on a block (let's call it block A). You have accessed block A in the past. There have been precisely 1027 different blocks accessed between your last access to block A and your current miss. Your block size is 64 bytes and you have a 32KB cache. What kind of miss was this? Select one: a. Capacity Miss b. Conflict Miss c. Compulsory MissSuppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? c) To which cache block will the memory address 0x000063FA map?
- QUESTION 22 Assume a cache has 16 entries. How many index bits are needed to address the cache? a. 2 b. 4 c. 5 d. 16 QUESTION 23 Which of the following statements about cache write policy is NOT true? a. A dirty bit is used to implement a write back approach. b. A cache entry with dirty bit = 1 means the data inside is safe to be replaced. c. A write back approach is not suitable for multiple processors accessing the same memory. d. A write back approach is typically faster than a write through approach. QUESTION 25 Which of the following statements is true of normalized scientific notation? a. 3.06 x 10^3 is in decimal normalized scientific notation b. 0.30 x 10^3 is in decimal normalized scientific notation c. 0.11 x 10^5 is in binary normalized scientific notation d. 10.01 x 10^5 is in binary normalized scientific notationHere is the question: A direct-mapped cache consists of 8 blocks. A byte-addressable main memory contains 4K blocks of eight bytes each. Access time for the cache is 20 ns and the time required to fill a cache slot from main memory is 300 ns. Assume a request is always started in sequential to cache and then to main memory. If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty. b) Compute the hit ratio for a program that loops 3 times from address 0 to 75 (base 10) in memory. For b, another example has been provided in regards to a previous problem: A direct-mapped cache consists of eight blocks. Main memory contains 4K blocks of eight words each. Access time for the cache is 22 ns and the time required to fill a cache slot from main memory is 300ns (this time will allow us to determine the block is missing and bring it into cache). Assume a request is always started in parallel to both cache and to…CA_10 Let the virtual address be V bits and the virtual addtess space be byte-addressable, the page size be P KB (and P is a power of 2), and the the main memory size be MM MB(where [MM MB]) is divide into [P KB]). (a) How large is the user's memory spac (b) How large is the main memory page frames? (c) How large is the page table (in number of table entries)? (d)How many of the virtual memory bits need to be translated? (e) How many bits will be produced if the virtual-to-pyysical address translation is "successful" (f) How many bits does a physical address have, and how are each of these bits obtained?
- CA_10 Let the virtual address be V bits and the virtual addtess space be byte-addressable, the page size be P KB (and P is a power of 2), and the the main memory size be MM MB(where [MM MB]) is divide into [P KB]). (d)How many of the virtual memory bits need to be translated? (e) How many bits will be produced if the virtual-to-pyysical address translation is "successful" (f) How many bits does a physical address have, and how are each of these bits obtained?Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. Could you hand draw the page table, if possible a) Suppose that the OS uses a two-level page table. Draw the page table. (Assume that frames 7 through 221 are free, so you can allocate space for the page table there.) In addition, suppose that the page-table directory storage comprises a whole number of consecutive full frames. (For examples: if the directory entry is 2 bytes, the entry’s storage comprises 1 frame; if the directory entry is 260 bytes, the entry’s storage comprises 2 consecutive frames.) b) What is the size of the two-level page tableCache Mapping Technique 1. Suppose a computer usingdirect-mapped cache has 2 bytes of byte=addressable main memory and a cache of32 blocks, where each cache block contains 16 bytes.a) How many blocksof main memory are there?b) What is theformat of a memory address as seen by the cache; that is, what are the sizes ofthe tag, block, and offset fields?c) To which cacheblock will the memory address 0x0DB63 map?2. Suppose a computer using fullyassociative cache has 2 bytes of byte-addressable main memory and a cache of128 blocks, where each cache block contains 64 bytes.a) How many blocksof main memory are there?b) What is theformat of a memory address as seen by the cache; that is, what are the sizes ofthe tag and offset fields?c) To which cacheblock will the memory address 0x01D872 map?3. A 2-way set-associative cacheconsists of four sets. Main memory contains 2K blocks of 8 bytes each and byte addressingis used.a) Show the mainmemory address format that allows us to map addresses from…
- 5 Consider the following code snippet: .datamyVar byte 4, 8, 5, 7.codemov esi, offset myVaradd esi, 2 What is the value at the memory location esi is pointing to? In other words, what value is referenced by [esi]? 6 Consider the following code snippet: .datamyArray word 01F2h, 1111h, 0ABDh, AAAAh.codemov ebx, offset myArrayadd ebx, 2 What is the value at the memory location ebx is pointing to? In other words, what value is referenced by [ebx]? 7 Consider the following code: .dataarray word 1, 2, 3, 4, 5.codemov eax, offset arraymov ecx, lengthof arrayloopstart:add byte ptr [eax], 1add eax, 2loop loopstart What are the values in the array after this code is finished executing?Draw a picture illustrating the contents of memory, given the following data declarations: You need to mark all the memory addresses. Assume that your data segment starts at 0x1000 in memory. Name: .asciiz "Jim Bond!"Age: .byte 24Numbers: .word 11, 22, 33Letter1: .asciiz 'M' In this format HexadecimalAddress, Hex Value, Character/Number/Symbol, Binary Value, Decimal Value ALREADY HAVE! marking all the memory addresses. Assuming that the data segment starts at 0x1000 in memory. The Memory Layout looks like Byte by Byte Address Data 0x1000 4a 0x1001 61 0x1002 6d 0x1003 65 0x1004 73 0x1005 00 0x1006 18 0x1007 00 0x1008 0b 0x1009 00 0x100a 00 0x100b 00 0x100c 21 0x100d 00 0x100e 00 0x100f 00 0x1010 14 0x1011 00 0x1012 00 0x1013 00 0x1014 4d arrow_forward Step 2 In mips 1 word is equal to 4 bytes. Address Data…Suppose that there is a file system with blocks of 512 bytes in size. For each inode, there are 20 direct blocks, 2 singly-indirect blocks, and 2 doubly-indirect blocks. The size of a pointer is 4 bytes. Calculate the maximum possible size of a file in bytes. Show your work.