1. Consider a CMOS NAND gate, as shown in Fig. 6-3, p. 159, of the textbook. The two inputs A and B are connected together, and tied to an input voltage VIN. The transistors have Kn = Kp, VDD = 2.0 V, Vtn = 0.5 V, and Vtp = -0.5 V. There is a point on the voltage transfer curve, VTC, where the NMOS transistors are at the saturation/nonsaturation boundary, and the PMOS transistors are in saturation. This occurs at the boundary between bias regions III and IV in Fig. 5-4, p. 128, in the text. Calculate Vin and Vout at this bias point. Remember that two parallel transistors have twice the drive state of a single transistor, and two series transistors have half the drive state of a single transistor. 2. Calculate the power supply current, IDD, at the bias point in problem 1. Take Kn = Kp = 400 µA/V².

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1. Consider a CMOS NAND gate, as shown in Fig. 6-3, p. 159, of the textbook. The
two inputs A and B are connected together, and tied to an input voltage VIN. The
transistors have Kn = Kp, VDD = 2.0 V, Vtn = 0.5 V, and Vtp = -0.5 V. There is a point
on the voltage transfer curve, VTC, where the NMOS transistors are at the
saturation/nonsaturation boundary, and the PMOS transistors are in saturation.
This occurs at the boundary between bias regions III and IV in Fig. 5-4, p. 128,
in the text. Calculate Vin and Vout at this bias point.
Remember that two parallel transistors have twice the drive state of a
single transistor, and two series transistors have half the drive state of a single
transistor.
2. Calculate the power supply current, IDD, at the bias point in problem 1. Take Kn =
Kp = 400 µA/V².
3. Repeat problem 1, but now consider the 2 input NOR gate, as shown in Fig. 6-6, p.
165, of the textbook.
Transcribed Image Text:1. Consider a CMOS NAND gate, as shown in Fig. 6-3, p. 159, of the textbook. The two inputs A and B are connected together, and tied to an input voltage VIN. The transistors have Kn = Kp, VDD = 2.0 V, Vtn = 0.5 V, and Vtp = -0.5 V. There is a point on the voltage transfer curve, VTC, where the NMOS transistors are at the saturation/nonsaturation boundary, and the PMOS transistors are in saturation. This occurs at the boundary between bias regions III and IV in Fig. 5-4, p. 128, in the text. Calculate Vin and Vout at this bias point. Remember that two parallel transistors have twice the drive state of a single transistor, and two series transistors have half the drive state of a single transistor. 2. Calculate the power supply current, IDD, at the bias point in problem 1. Take Kn = Kp = 400 µA/V². 3. Repeat problem 1, but now consider the 2 input NOR gate, as shown in Fig. 6-6, p. 165, of the textbook.
VDD
C
A B C
A
1
CL
1
B
1
1
1
1
(a)
(b)
1.8
1.6
1.4
1.2
1
S 0.8
Region I
0.6-
Region II
Region IV
Region V
0.4
0.2
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Vin (V)
FIGURE 5-4.
Vo versus Vin voltage transfer curve (VTC) with five bias states. The input voltage Vin is swept
from 0 – VDp while Vo is measured.
(A) A
Region III
Transcribed Image Text:VDD C A B C A 1 CL 1 B 1 1 1 1 (a) (b) 1.8 1.6 1.4 1.2 1 S 0.8 Region I 0.6- Region II Region IV Region V 0.4 0.2 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Vin (V) FIGURE 5-4. Vo versus Vin voltage transfer curve (VTC) with five bias states. The input voltage Vin is swept from 0 – VDp while Vo is measured. (A) A Region III
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