2. Consider two processors P1 and P2 with four types of instructions as listed in Table 1. Assume that a program with a dynamic instruction count of 106 instructions such that the instructions are divided into the classes as follows: 10% class A, 20% class B, 50% class C, and 20% class D. a. Which implementation (P1 or P2) is faster? b. What is the overall CPI for each implementation P1 and P2? c. Find the clock cycles required for both processors. CPU/CPI Class A Class B Class C Class D P1(2.5 GHz) 1 2 3 3 P2(3.0 GHz) 2 4 2 3 Table 1 Clock per instruction for each class off instruction

2. Consider two processors P1 and P2 with four types of instructions as listed in Table 1. Assume that a program with a dynamic instruction count of 106 instructions such that the instructions are divided into the classes as follows: 10% class A, 20% class B, 50% class C, and 20% class D. a. Which implementation (P1 or P2) is faster? b. What is the overall CPI for each implementation P1 and P2? c. Find the clock cycles required for both processors. CPU/CPI Class A Class B Class C Class D P1(2.5 GHz) 1 2 3 3 P2(3.0 GHz) 2 4 2 3 Table 1 Clock per instruction for each class off instruction

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Suppose the implementation of an instruction set architecture uses three classes of instructions, which are called A, B, and C. The total dynamic instruction count is 1 x 10^7 and the processor's clock rate is 2.5 GHz. Details for the three classes are given in the table below: Class CPI % of instructions A 1 20% 50% C 3 30% Complete the following table. Express all answers in scientific notation and round to two decimal places, when needed. Class Instruction Count Number of Clock Cycles х 10^ x 10^ A х 10^ х 10^ x 10^ х 10^ C
Assume a 3GHz processor executes three classes of instructions(A, B, C).i. Calculate the average CPI for this sequence of program.ii. Calculate the execution time for this sequence of program.iii. If we use a system with four same processors, there will bespeed up by a factor of 4 for classes A and C, but class B willremain unaffected. Calculate the new execution time for thissystem. What is the overall speed up? Class A B C CPI for class 4 2 10 IC in sequence 100 200 300
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. Consider a system that has multiple processors where eachprocessor has its own cache, but main memory is shared among allprocessors.1. a) Which cache write policy would you use?2. b) The cache coherency problem. With regard to the systemjust described, what problems are caused if a processor has acopy of memory block A in its cache and a second processor,also having a copy of A in its cache, then updates mainmemory block A? Can you think of a way (perhaps morethan one) of preventing this situation, or lessening itseffects?
Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3.1 GHz clock rate and a CPI (cycles per instruction) of 1.6. P2 has a 2.4 GHz clock rate and a CPI of 1.2. P3 has a 4.0 GHz clock rate and has a CPI of 2.0 If you could answer these id appreciate that greatly. a.Which processor has the highest performance expressed in instructions per second? b.If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions. c.We are trying to reduce the execution time by 30% but this leads to an increase of 20% in the CPI. What clock rate should we have to get this time reduction?
Suppose that each of the 4 processors in a shared memory multi-processor system is rated at 400 MIPS. A program contains a purely sequential part that accounts for 22% of the program’s execution time on a single processor. The remaining code can be partitioned into three independent parts (A, B, and C). Running on a single processor, part A accounts for 30% of the program’s execution time, part B accounts for 18%, and part C accounts for 30%. What is the apparent MIPS rating for the program if it is run on the 4-processor system and the sequential part must be completed before any of the remaining independent parts (A, B or C) can run in parallel?
Question: Suppose a program of 600 instructions runs on a 2 GHz processor. The frequency of instructions and the clock cycle counts per instruction are given as follows. What is the average CPI of this instruction mix? Operation Frequency Clock Cycles ALU operations 55% 1 Loads/Stores 30% 2 Branches 15% 3 Question: Continue from the previous question. What is the CPU time of the program in nanoseconds? Question: Suppose a processor P has a 2.5 GHz clock rate and a CPI of 1.5. If the processor executes a program in 3 microseconds, find the number of instructions in the program.
Consider two different implementations of the same instruction set architecture. The instructions can be divided into three classes according to their CPI (class A, B, C). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, and 3, and P2 with a clock rate of 3 GHz and CPIs of 2, 2, 2. Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows: 30% class A, 30% class B, 40% class C, which implementation is faster? What is the global CPI for each implementation? Find the clock cycles required in both cases.
a) Suppose two threads T1 and T2 are running concurrently in the same process with a single CPU. Suppose T1 does “Load X into register R1” machine instruction. Then the CPU scheduler switches the CPU to T2. Will T2 see the same vaue of R1 as loaded here by T1? (YES or NO)? Explain in less than 50 words. Be specific. (b) Suppose two threads T1 and T2 are running concurrently in the same process with a single CPU. Is it possible to have a moment (time instant) where both threads have made a request to Memory Unit to read some data (ex. as part of a “Load … into register …” instruction) and Memory Unit has not yet completed either of these two requests? Explain in less than 50 words.
17. Consider the following hypothetical instruction: SubMem R1, mem1, mem2 This instruction works as follows: \[ \mathrm{R} 1 \leftarrow \text { [mem1] - [mem2] } \] In a multi-cycle datapath implementation, this instruction will: a. Use the MDR twice b. Use the ALU once c. Use the "shift to left" unit twice d. None of the above Answer: B 18. Consider the following hypothetical instruction: Mems mem1, R1, mem2 This instruction works as follows: \[ \text { [mem1] } \leftarrow \mathrm{R} 1 \text { - [mem2] } \] One of the following is correct about this instruction: a. It will not need theBregister b. It will require priting into MDR twice c. It will require writing into the ALUout three times d. None of the above Answer: A 19. By comparing the hypothetical instructions given in Questions (17) and (18), if we run these instructions on the same processor, then one of the following is correct: a. Both instructions have the same CPI b. Mems executes faster than SubMem c. SubMem executes…
The table below shows instruction-type breakdown for different programs. Using this data, you will be exploring the performance trade-offs for different changes made to an MIPS processor. Class A Class B Class C Class D Total Program1 90 100 30 10 ? Program2 110 70 20 20 ? Calculate the total instructions required by each of the programs. Assuming that Class A take 1 cycle (CPI) , B and C instructions take 2 cycles, and D take 3 cycles, find the execution time for both the programs on a 3 GHz Processor. What is the speedup if the number of A instruction can be reduced by half and D instructions increased to double? (for both the programs)
When a program is adapted to run on multiple processors in a multiprocessor system, the execution time on each processor is comprised of computing time and the overhead time required for locked critical sections and/or to send data from one processor to another. Assume a program requires t = 100 s of execution time on one processor. When run p processors, each processor requires t/p s, as well as an additional 4 s of overhead, irrespective of the number of processors. Compute the per-processor execution time for 2, 4, 8, 16, 32, 64, and 128 processors. For each case, list the corresponding speedup relative to a single processor and the ratio between actual speedup versus ideal speedup (speedup if there was no overhead).